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Searched refs:_VPU_MIU_SetReqMask (Results 1 – 25 of 31) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/vpu/
H A DhalVPU.c136 #define _VPU_MIU_SetReqMask( miu_clients, mask ) \ macro
294 _VPU_MIU_SetReqMask( VPU_D_RW , bEnable ); in HAL_VPU_MIU_RW_Protect()
295 _VPU_MIU_SetReqMask( VPU_Q_RW , bEnable ); in HAL_VPU_MIU_RW_Protect()
296 _VPU_MIU_SetReqMask( VPU_I_R , bEnable ); in HAL_VPU_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/vpu/
H A DhalVPU.c136 #define _VPU_MIU_SetReqMask( miu_clients, mask ) \ macro
294 _VPU_MIU_SetReqMask( VPU_D_RW , bEnable ); in HAL_VPU_MIU_RW_Protect()
295 _VPU_MIU_SetReqMask( VPU_Q_RW , bEnable ); in HAL_VPU_MIU_RW_Protect()
296 _VPU_MIU_SetReqMask( VPU_I_R , bEnable ); in HAL_VPU_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/vpu/
H A DhalVPU.c136 #define _VPU_MIU_SetReqMask( miu_clients, mask ) \ macro
294 _VPU_MIU_SetReqMask( VPU_D_RW , bEnable ); in HAL_VPU_MIU_RW_Protect()
295 _VPU_MIU_SetReqMask( VPU_Q_RW , bEnable ); in HAL_VPU_MIU_RW_Protect()
296 _VPU_MIU_SetReqMask( VPU_I_R , bEnable ); in HAL_VPU_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/vpu/
H A DhalVPU.c136 #define _VPU_MIU_SetReqMask( miu_clients, mask ) \ macro
294 _VPU_MIU_SetReqMask( VPU_D_RW , bEnable ); in HAL_VPU_MIU_RW_Protect()
295 _VPU_MIU_SetReqMask( VPU_Q_RW , bEnable ); in HAL_VPU_MIU_RW_Protect()
296 _VPU_MIU_SetReqMask( VPU_I_R , bEnable ); in HAL_VPU_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/vpu/
H A DhalVPU.c136 #define _VPU_MIU_SetReqMask( miu_clients, mask ) \ macro
294 _VPU_MIU_SetReqMask( VPU_D_RW , bEnable ); in HAL_VPU_MIU_RW_Protect()
295 _VPU_MIU_SetReqMask( VPU_Q_RW , bEnable ); in HAL_VPU_MIU_RW_Protect()
296 _VPU_MIU_SetReqMask( VPU_I_R , bEnable ); in HAL_VPU_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/vpu/
H A DhalVPU.c136 #define _VPU_MIU_SetReqMask( miu_clients, mask ) \ macro
294 _VPU_MIU_SetReqMask( VPU_D_RW , bEnable ); in HAL_VPU_MIU_RW_Protect()
295 _VPU_MIU_SetReqMask( VPU_Q_RW , bEnable ); in HAL_VPU_MIU_RW_Protect()
296 _VPU_MIU_SetReqMask( VPU_I_R , bEnable ); in HAL_VPU_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/vpu_ex/
H A DhalVPU_EX.c226 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
1836 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1837 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1838 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/vpu_ex/
H A DhalVPU_EX.c226 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
1836 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1837 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1838 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/vpu_ex/
H A DhalVPU_EX.c226 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
1836 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1837 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1838 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/vpu_ex/
H A DhalVPU_EX.c226 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
1836 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1837 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1838 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/vpu_ex/
H A DhalVPU_EX.c226 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
1836 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1837 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1838 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/vpu_ex/
H A DhalVPU_EX.c226 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
1836 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1837 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1838 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/vpu_ex/
H A DhalVPU_EX.c226 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
1836 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1837 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1838 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/vpu_ex/
H A DhalVPU_EX.c226 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
1836 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1837 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1838 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/vpu_ex/
H A DhalVPU_EX.c247 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
1867 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1868 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1869 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/vpu_ex/
H A DhalVPU_EX.c247 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
1867 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1868 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
1869 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maldives/vpu_v3/
H A DhalVPU_EX.c251 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
2289 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2290 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2291 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DhalVPU_EX.c267 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
2381 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2382 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2383 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/vpu_v3/
H A DhalVPU_EX.c263 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
2429 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2430 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2431 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/vpu_v3/
H A DhalVPU_EX.c268 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
2448 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2449 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2450 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A DhalVPU_EX.c275 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
2411 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2412 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2413 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DhalVPU_EX.c267 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
2382 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2383 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2384 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A DhalVPU_EX.c267 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
2366 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2367 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2368 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/vpu_v3/
H A DhalVPU_EX.c273 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
2502 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2503 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2504 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DhalVPU_EX.c280 #define _VPU_MIU_SetReqMask(miu_clients, mask) \ macro
2520 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2521 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable); in HAL_VPU_EX_MIU_RW_Protect()
2522 _VPU_MIU_SetReqMask(VPU_I_R, bEnable); in HAL_VPU_EX_MIU_RW_Protect()

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