1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #else
103 #include <string.h>
104 #endif
105
106 #if defined(REDLION_LINUX_KERNEL_ENVI)
107 #include "drvHVD_Common.h"
108 #else
109 #include "MsCommon.h"
110 #endif
111
112 #include "MsOS.h"
113 #include "asmCPU.h"
114
115
116 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
117
118 // Internal Definition
119 #include "regVPU_EX.h"
120 #include "halVPU_EX.h"
121 #include "halCHIP.h"
122 #include "drvSYS.h"
123 #if defined(VDEC3)
124 #include "../../../drv/hvd_v3/drvHVD_def.h"
125 #include "../hvd_v3/fwHVD_if.h"
126 #include "../mvd_v3/mvd4_interface.h"
127 #include "halHVD_EX.h"
128 #else
129 #include "../../../drv/hvd_v3/drvHVD_def.h"
130 #include "../hvd_v3/fwHVD_if.h"
131 #include "../mvd_v3/mvd4_interface.h"
132 #endif
133 #include "controller.h"
134
135 #if (ENABLE_DECOMPRESS_FUNCTION == TRUE)
136 #include "ms_decompress.h"
137 #include "ms_decompress_priv.h"
138 #endif
139 #include "../../drv/mbx/apiMBX_St.h"
140 #include "../../drv/mbx/apiMBX.h"
141
142 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
143 #include "drvSERFLASH.h"
144 #define HVD_FLASHcpy(DESTADDR, SRCADDR, LEN, Flag) MDrv_SERFLASH_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), (Flag), SPIDMA_OPCFG_DEF)
145 #endif
146
147 #ifdef MSOS_TYPE_LINUX_KERNEL
148 #define VPRINTF printk
149 #else
150 #ifndef ANDROID
151 #define VPRINTF printf
152 #else
153 #include <sys/mman.h>
154 #include <cutils/ashmem.h>
155 #include <cutils/log.h>
156 #define VPRINTF ALOGD
157 #endif
158 #endif
159
160
161 //-------------------------------------------------------------------------------------------------
162 // Driver Compiler Options
163 //-------------------------------------------------------------------------------------------------
164
165
166 //-------------------------------------------------------------------------------------------------
167 // Local Defines
168 //-------------------------------------------------------------------------------------------------
169 #define VPU_CTL_INTERFACE_VER 0x00000001 //the interface version of VPU driver
170
171 #define VPU_MIU1BASE_ADDR 0x40000000UL //Notice: this define must be comfirm with designer
172 #ifdef VDEC3
173 #define MAX_EVD_BBU_COUNT 1 // This definition is chip-dependent.
174 #define MAX_HVD_BBU_COUNT 2 // The Chip after Monaco(included) have two EVD BBU, must check this definition when bring up
175 #define MAX_MVD_SLQ_COUNT 2
176 #define MAX_SUPPORT_DECODER_NUM 16
177 #else
178 #define MAX_SUPPORT_DECODER_NUM 2
179 #endif
180 typedef enum
181 {
182 E_VDEC_EX_REE_TO_TEE_MBX_MSG_NULL,
183 E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode,
184 E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR,
185 } VDEC_REE_TO_TEE_MBX_MSG_TYPE;
186
187
188 typedef enum
189 {
190 E_VDEC_EX_TEE_TO_REE_MBX_MSG_NULL,
191 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID,
192 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE,
193 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS,
194 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL
195 } VDEC_TEE_TO_REE_MBX_ACK_TYPE;
196
197 typedef enum
198 {
199 E_VPU_UART_CTRL_DISABLE = BIT(4),
200 E_VPU_UART_CTRL_ERR = BIT(0),
201 E_VPU_UART_CTRL_INFO = BIT(1),
202 E_VPU_UART_CTRL_DBG = BIT(2),
203 E_VPU_UART_CTRL_FW = BIT(3),
204 E_VPU_UART_CTRL_MUST = BIT(4),
205 E_VPU_UART_CTRL_TRACE = BIT(5),
206 } VPU_EX_UartCtrl;
207
208 typedef struct
209 {
210 HAL_VPU_StreamId eStreamId;
211 VPU_EX_DecoderType eDecodertype;
212 } VPU_EX_Stream;
213
214 typedef struct
215 {
216 MS_BOOL bSTCSetMode;
217 MS_U32 u32STCIndex;
218 } VPU_EX_STC;
219
220 #define VPU_MSG_ERR(format, args...) \
221 do \
222 { \
223 if (u32VpuUartCtrl & E_VPU_UART_CTRL_ERR) \
224 { \
225 printf("[VPU][ERR]%s:", __FUNCTION__); \
226 printf(format, ##args); \
227 } \
228 } while (0)
229
230 #define VPU_MSG_DBG(format, args...) \
231 do \
232 { \
233 if (u32VpuUartCtrl & E_VPU_UART_CTRL_DBG) \
234 { \
235 printf("[VPU][DBG]%s:", __FUNCTION__); \
236 printf(format, ##args); \
237 } \
238 } while (0)
239
240 #define VPU_MSG_INFO(format, args...) \
241 do \
242 { \
243 if (u32VpuUartCtrl & E_VPU_UART_CTRL_INFO) \
244 { \
245 printf("[VPU][INF]%s:", __FUNCTION__); \
246 printf(format, ##args); \
247 } \
248 } while (0)
249
250 //------------------------------ MIU SETTINGS ----------------------------------
251 #define _MaskMiuReq_VPU_D_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1))
252 #define _MaskMiuReq_VPU_Q_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1))
253 #define _MaskMiuReq_VPU_I_R(m) _VPU_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(2))
254
255 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1))
256 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1))
257 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(2))
258
259 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
260 #define VPU_Q_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
261 #define VPU_I_R_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(2)) == BIT(2))
262
263 #define _VPU_MIU_SetReqMask(miu_clients, mask) \
264 do { \
265 if (miu_clients##_ON_MIU1 == 0) \
266 _MaskMiuReq_##miu_clients(mask); \
267 else \
268 _MaskMiu1Req_##miu_clients(mask); \
269 } while(0)
270
271 #if ENABLE_VPU_MUTEX_PROTECTION
272 static MS_S32 s32VPUMutexID = -1;
273 MS_U8 _u8VPU_Mutex[] = { "VPU_Mutex" };
274
275 #define _HAL_VPU_MutexCreate() \
276 if (s32VPUMutexID < 0) \
277 { \
278 s32VPUMutexID = MsOS_CreateMutex(E_MSOS_FIFO,(char*)_u8VPU_Mutex, MSOS_PROCESS_SHARED); \
279 }
280
281 #define _HAL_VPU_MutexDelete() \
282 if (s32VPUMutexID >= 0) \
283 { \
284 MsOS_DeleteMutex(s32VPUMutexID); \
285 s32VPUMutexID = -1; \
286 }
287
288 #define _HAL_VPU_Entry() \
289 if (s32VPUMutexID >= 0) \
290 { \
291 if (!MsOS_ObtainMutex(s32VPUMutexID, VPU_DEFAULT_MUTEX_TIMEOUT)) \
292 { \
293 printf("[HAL VPU][%06d] Mutex taking timeout\n", __LINE__); \
294 } \
295 }
296
297 #define _HAL_VPU_Return(_ret) \
298 { \
299 if (s32VPUMutexID >= 0) \
300 { \
301 MsOS_ReleaseMutex(s32VPUMutexID); \
302 } \
303 return _ret; \
304 }
305
306 #define _HAL_VPU_Release() \
307 { \
308 if (s32VPUMutexID >= 0) \
309 { \
310 MsOS_ReleaseMutex(s32VPUMutexID); \
311 } \
312 }
313 #else
314 #define _HAL_VPU_MutexCreate()
315 #define _HAL_VPU_MutexDelete()
316 #define _HAL_VPU_Entry()
317 #define _HAL_VPU_Return(_ret) {return _ret;}
318 #define _HAL_VPU_Release()
319 #endif
320
321 #define VPU_FW_MEM_OFFSET 0x100000UL // 1M
322 #define VPU_CMD_TIMEOUT 1000 // 1 sec
323
324 //-------------------------------------------------------------------------------------------------
325 // Local Structures
326 //-------------------------------------------------------------------------------------------------
327 typedef struct _VPU_HWInitFunc
328 {
329 MS_BOOL (*pfMVDHW_Init)(void);
330 MS_BOOL (*pfMVDHW_Deinit)(void);
331 MS_BOOL (*pfHVDHW_Init)(MS_U32 u32Arg);
332 MS_BOOL (*pfHVDHW_Deinit)(void);
333 } VPU_HWInitFunc;
334
335 typedef struct
336 {
337 MS_U32 u32ApiHW_Version; //<Version of current structure>
338 MS_U16 u16ApiHW_Length; //<Length of this structure>
339
340 MS_U8 u8Cap_Support_Decoder_Num;
341
342 MS_BOOL bCap_Support_MPEG2;
343 MS_BOOL bCap_Support_H263;
344 MS_BOOL bCap_Support_MPEG4;
345 MS_BOOL bCap_Support_DIVX311;
346 MS_BOOL bCap_Support_DIVX412;
347 MS_BOOL bCap_Support_FLV;
348 MS_BOOL bCap_Support_VC1ADV;
349 MS_BOOL bCap_Support_VC1MAIN;
350
351 MS_BOOL bCap_Support_RV8;
352 MS_BOOL bCap_Support_RV9;
353 MS_BOOL bCap_Support_H264;
354 MS_BOOL bCap_Support_AVS;
355 MS_BOOL bCap_Support_AVS_PLUS;
356 MS_BOOL bCap_Support_MJPEG;
357 MS_BOOL bCap_Support_MVC;
358 MS_BOOL bCap_Support_VP8;
359 MS_BOOL bCap_Support_VP9;
360 MS_BOOL bCap_Support_HEVC;
361
362 /*New HW Cap and Feature add in struct at the end*/
363 }VDEC_HwCap;
364
365 //-------------------------------------------------------------------------------------------------
366 // Local Functions Prototype
367 //-------------------------------------------------------------------------------------------------
368 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType);
369 static MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id);
370 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo);
371
372 //-------------------------------------------------------------------------------------------------
373 // Global Variables
374 //-------------------------------------------------------------------------------------------------
375 extern HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg);
376 extern MS_BOOL HAL_MVD_InitHW(void);
377 extern MS_BOOL HAL_MVD_DeinitHW(void);
378 extern MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType);
379 extern MS_BOOL HAL_HVD_EX_DeinitHW(void);
380 extern void HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id);
381 extern MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id);
382 #if SUPPORT_G2VP9 && defined(VDEC3)
383 extern MS_BOOL HAL_VP9_EX_DeinitHW(void);
384 #endif
385 #if defined (__aeon__)
386 static MS_VIRT u32VPURegOSBase = 0xA0000000UL;
387 #else
388 static MS_VIRT u32VPURegOSBase = 0xBF200000UL;
389 #endif
390
391 //-------------------------------------------------------------------------------------------------
392 // Local Variables
393 //-------------------------------------------------------------------------------------------------
394 #if 0
395
396 static MS_BOOL _bVPUPowered = FALSE;
397 static MS_BOOL _bVPURsted = FALSE;
398 static MS_BOOL _bVPUSingleMode = FALSE;
399 static VPU_EX_DecModCfg _stVPUDecMode;
400
401 static MS_U8 u8TaskCnt = 0;
402
403 static MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
404
405 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
406 static VPU_EX_Stream _stVPUStream[] =
407 {
408 {E_HAL_VPU_MAIN_STREAM0, E_VPU_EX_DECODER_NONE},
409 {E_HAL_VPU_SUB_STREAM0, E_VPU_EX_DECODER_NONE},
410 };
411 static VPU_HWInitFunc stHWInitFunc =
412 {
413 &HAL_MVD_InitHW,
414 &HAL_MVD_DeinitHW,
415 &HAL_HVD_EX_InitHW,
416 &HAL_HVD_EX_DeinitHW,
417 };
418
419 #endif
420
421 #if VPU_ENABLE_EMBEDDED_FW_BINARY
422 static const MS_U8 u8HVD_FW_Binary[] = {
423 #include "fwVPU.dat"
424 };
425
426 #if HVD_ENABLE_RV_FEATURE
427 static const MS_U8 u8HVD_VLC_Binary[] = {
428 #include "fwVPU_VLC.dat"
429 };
430 #endif
431 #endif
432
433
434 #ifdef VDEC3
435 typedef struct
436 {
437 MS_BOOL bTSP;
438 MS_U8 u8RegSetting; //NAL_TBL: BIT(0), ES_BUFFER: BIT(1)
439 MS_U32 u32Used;
440 } BBU_STATE;
441
442 typedef struct
443 {
444 MS_BOOL bTSP;
445 MS_BOOL bUsedbyMVD;
446 MS_U32 u32Used;
447 } SLQ_STATE;
448 #endif
449
450 typedef struct
451 {
452 MS_BOOL _bVPUPowered;
453 MS_BOOL _bVPURsted;
454 MS_BOOL _bVPUSingleMode;
455 VPU_EX_DecModCfg _stVPUDecMode;
456 MS_U8 u8TaskCnt;
457 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
458 #ifdef VDEC3
459 VPU_EX_Stream _stVPUStream[MAX_SUPPORT_DECODER_NUM];
460 #else
461 VPU_EX_Stream _stVPUStream[2];
462 #endif
463
464 VPU_HWInitFunc stHWInitFunc;
465
466 MS_BOOL bVpuExReloadFW;
467 MS_BOOL bVpuExLoadFWRlt;
468 MS_VIRT u32VPUSHMAddr; //PA
469 MS_BOOL bEnableVPUSecureMode;
470
471 MS_VIRT u32FWShareInfoAddr[MAX_SUPPORT_DECODER_NUM];
472 MS_BOOL bEnableDymanicFBMode;
473 MS_PHY u32DynamicFBAddress;
474 MS_U32 u32DynamicFBSize;
475 #ifdef VDEC3
476 MS_VIRT u32FWCodeAddr;
477 MS_VIRT u32BitstreamAddress[MAX_SUPPORT_DECODER_NUM];
478
479 BBU_STATE stHVD_BBU_STATE[MAX_HVD_BBU_COUNT];
480 BBU_STATE stEVD_BBU_STATE[MAX_EVD_BBU_COUNT];
481 SLQ_STATE stMVD_SLQ_STATE[MAX_MVD_SLQ_COUNT];
482
483 MS_U8 u8HALId[MAX_SUPPORT_DECODER_NUM];
484 #endif
485 MS_U8 u8ForceRst;
486 VPU_EX_STC _stVPUSTCMode[MAX_SUPPORT_DECODER_NUM];
487 } VPU_Hal_CTX;
488
489 //global variables
490 VPU_Hal_CTX* pVPUHalContext = NULL;
491 VPU_Hal_CTX gVPUHalContext;
492 MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
493 MS_BOOL bVPUMbxInitFlag = 0;
494 MS_U8 u8VPUMbxMsgClass = 0;
495 MBX_Msg VPUReeToTeeMbxMsg;
496 MBX_Msg VPUTeeToReeMbxMsg;
497
498 //-------------------------------------------------------------------------------------------------
499 // Debug Functions
500 //-------------------------------------------------------------------------------------------------
501 #if 0
502 static MBX_ROLE_ID _VPU_EX_CpuIdMapRoleId(MBX_CPU_ID id)
503 {
504 MBX_ROLE_ID res = E_MBX_ROLE_MAX;
505 switch(id)
506 {
507 case E_MBX_CPU_PM :res = E_MBX_ROLE_HK;break;
508 case E_MBX_CPU_AEON :res = E_MBX_ROLE_CP;break;
509 //case E_MBX_CPU_MIPS :
510 //case E_MBX_CPU_R2M :
511 case E_MBX_CPU_MIPS_VPE0 :res = E_MBX_ROLE_PM;break;
512 case E_MBX_CPU_MIPS_VPE1 :res = E_MBX_ROLE_MAX;break;
513 default:break;
514 }
515 return res;
516 }
517 #endif
518
519 //-------------------------------------------------------------------------------------------------
520 // Local Functions
521 //-------------------------------------------------------------------------------------------------
522
_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)523 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
524 {
525 #if HVD_ENABLE_RV_FEATURE
526 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
527 {
528 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
529 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
530 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
531
532 if (pVlcCfg->u32BinSize)
533 {
534 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
535
536 MS_U32 u32Start;
537 MS_U32 u32StartOffset;
538 MS_U8 u8MiuSel;
539
540 // Get MIU selection and offset from physical address = 0x30000000
541 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pVlcCfg->u32FrameBufAddr);
542
543
544 if(u8MiuSel == E_CHIP_MIU_0)
545 cpyflag = E_SPIDMA_DEV_MIU0;
546 else if(u8MiuSel == E_CHIP_MIU_1)
547 cpyflag = E_SPIDMA_DEV_MIU1;
548 else if(u8MiuSel == E_CHIP_MIU_2)
549 cpyflag = E_SPIDMA_DEV_MIU2;
550
551 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
552 {
553 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
554 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
555
556 return FALSE;
557 }
558 }
559 else
560 {
561 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
562 return FALSE;
563 }
564 #else
565 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
566 return FALSE;
567 #endif
568 }
569 else
570 {
571 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
572 {
573 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
574 {
575 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
576 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
577
578 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
579 BDMA_Result bdmaRlt;
580 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
581
582 u32DstAdd = pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset;
583 u32SrcAdd = pVlcCfg->u32BinAddr;
584 u32tabsize = pVlcCfg->u32BinSize;
585 //bdmaRlt = MDrv_BDMA_MemCopy(u32SrcAdd, u32DstAdd, SLQ_TBL_SIZE);
586 MsOS_FlushMemory();
587 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
588
589 if (E_BDMA_OK != bdmaRlt)
590 {
591 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
592 }
593 #else
594 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
595 #endif
596 }
597 else
598 {
599 VPU_MSG_ERR
600 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
601 return FALSE;
602 }
603 }
604 else
605 {
606 #if VPU_ENABLE_EMBEDDED_FW_BINARY
607 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
608 MS_U8 *pu8HVD_VLC_Binary;
609
610 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
611
612 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
613 pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset, ((MS_U32) pu8HVD_VLC_Binary),
614 (MS_U32) sizeof(u8HVD_VLC_Binary));
615
616 HVD_memcpy((void *) (pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset),
617 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
618 #else
619 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
620 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long)u8HVD_VLC_Binary,
621 (MS_U32) sizeof(u8HVD_VLC_Binary));
622
623 HVD_memcpy(pVlcCfg->u32DstAddr, ((unsigned long)u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
624 #endif
625 #else
626 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
627 return FALSE;
628 #endif
629 }
630 }
631 #endif
632
633 return TRUE;
634 }
635
636 //Notice: this function must be consistent with _stVPUStream[]
_VPU_EX_GetOffsetIdx(MS_U32 u32Id)637 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id)
638 {
639 MS_U8 u8OffsetIdx = 0;
640 MS_U8 u8VSidBaseMask = 0xF0;
641 HAL_VPU_StreamId eVSidBase = (HAL_VPU_StreamId)(u32Id & u8VSidBaseMask);
642
643 switch (eVSidBase)
644 {
645 case E_HAL_VPU_MAIN_STREAM_BASE:
646 {
647 u8OffsetIdx = 0;
648 break;
649 }
650 case E_HAL_VPU_SUB_STREAM_BASE:
651 {
652 u8OffsetIdx = 1;
653 break;
654 }
655 case E_HAL_VPU_MVC_STREAM_BASE:
656 {
657 u8OffsetIdx = 0;
658 break;
659 }
660 #ifdef VDEC3
661 case E_HAL_VPU_N_STREAM_BASE:
662 {
663 u8OffsetIdx = u32Id & 0x0F;
664 break;
665 }
666 #endif
667 default:
668 {
669 u8OffsetIdx = 0;
670 break;
671 }
672 }
673
674 /*
675 VPU_MSG_DBG("u32Id=0x%lx, eVSidBase=0x%x, u8OffsetIdx=0x%x\n",
676 u32Id, eVSidBase, u8OffsetIdx);
677 */
678 return u8OffsetIdx;
679 }
680
HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)681 MS_U8 HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)
682 {
683 return _VPU_EX_GetOffsetIdx(u32Id);
684 }
685
_VPU_EX_Context_Init(void)686 static void _VPU_EX_Context_Init(void)
687 {
688 #ifdef VDEC3
689 MS_U8 i;
690
691 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
692 {
693 pVPUHalContext->_stVPUStream[i].eStreamId = E_HAL_VPU_N_STREAM0 + i;
694 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
695 }
696
697 for (i = 0; i < MAX_HVD_BBU_COUNT; i++)
698 {
699 pVPUHalContext->stHVD_BBU_STATE[i].bTSP = FALSE;
700 pVPUHalContext->stHVD_BBU_STATE[i].u32Used = 0;
701 }
702
703 for (i = 0; i < MAX_EVD_BBU_COUNT; i++)
704 {
705 pVPUHalContext->stEVD_BBU_STATE[i].bTSP = FALSE;
706 pVPUHalContext->stEVD_BBU_STATE[i].u32Used = 0;
707 }
708
709 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
710 {
711 pVPUHalContext->stMVD_SLQ_STATE[i].bTSP = FALSE;
712 pVPUHalContext->stMVD_SLQ_STATE[i].bUsedbyMVD= FALSE;
713 pVPUHalContext->stMVD_SLQ_STATE[i].u32Used = 0;
714 }
715 #else
716 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MAIN_STREAM0;
717 pVPUHalContext->_stVPUStream[1].eStreamId = E_HAL_VPU_SUB_STREAM0;
718 #endif
719 pVPUHalContext->bVpuExReloadFW = TRUE;
720 pVPUHalContext->u8ForceRst = 0;
721
722 }
723
HAL_VPU_EX_ForceSwRst(void)724 void HAL_VPU_EX_ForceSwRst(void)
725 {
726 pVPUHalContext->u8ForceRst = 1;
727 }
728
_VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo * pTaskInfo)729 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo)
730 {
731 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
732 MS_U8 u8OffsetIdx = 0;
733
734 if (NULL == pTaskInfo)
735 {
736 return eCmd;
737 }
738
739 u8OffsetIdx = _VPU_EX_GetOffsetIdx(pTaskInfo->u32Id);
740
741 VPU_MSG_INFO("input TaskInfo u32Id=0x%08x eVpuId=0x%x src=0x%x dec=0x%x\n",
742 pTaskInfo->u32Id, pTaskInfo->eVpuId, pTaskInfo->eSrcType, pTaskInfo->eDecType);
743
744 #ifdef VDEC3
745 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
746 {
747 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
748 {
749 eCmd = E_NST_CMD_TASK_MVD_TSP;
750 }
751 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
752 {
753 eCmd = E_NST_CMD_TASK_MVD_SLQ;
754 }
755 }
756 #else
757 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
758 {
759 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
760 {
761 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_TSP : E_DUAL_CMD_TASK1_MVD_TSP;
762 }
763 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
764 {
765 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_SLQ : E_DUAL_CMD_TASK1_MVD_SLQ;
766 }
767 }
768 #endif
769 #ifdef VDEC3
770 #if SUPPORT_G2VP9
771 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
772 #else
773 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
774 #endif
775 {
776 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
777 {
778 eCmd = E_NST_CMD_TASK_HVD_TSP;
779 }
780 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
781 {
782 eCmd = E_NST_CMD_TASK_HVD_BBU;
783 }
784 }
785 #else
786 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
787 {
788 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
789 {
790 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_TSP : E_DUAL_CMD_TASK1_HVD_TSP;
791 }
792 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
793 {
794 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_BBU : E_DUAL_CMD_TASK1_HVD_BBU;
795 }
796 }
797 #endif
798
799 VPU_MSG_INFO("output: eCmd=0x%x offsetIdx=0x%x\n", eCmd, u8OffsetIdx);
800 return eCmd;
801 }
802
_VPU_EX_InitHW(VPU_EX_TaskInfo * pTaskInfo)803 static MS_BOOL _VPU_EX_InitHW(VPU_EX_TaskInfo *pTaskInfo)
804 {
805 if (!pTaskInfo)
806 {
807 VPU_MSG_ERR("null input\n");
808 return FALSE;
809 }
810
811 //Check if we need to init MVD HW
812 if ((E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType) ||
813 (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType))
814 {
815 //Init HW
816 if (FALSE == HAL_VPU_EX_MVDInUsed())
817 {
818 if (TRUE != HAL_MVD_InitHW())
819 {
820 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
821 return FALSE;
822 }
823 }
824 else
825 {
826 VPU_MSG_ERR("(%d): do nothing\n", __LINE__);
827 }
828 }
829
830 //MVD use sub mvop
831 if((E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType) &&
832 #ifdef VDEC3
833 (pTaskInfo->u8HalId == 1) )
834 #else
835 (E_HAL_VPU_SUB_STREAM0 == pTaskInfo->eVpuId))
836 #endif
837 {
838 VPU_MSG_ERR("Force turn on HVD\n");
839 if(!HAL_VPU_EX_HVDInUsed())
840 {
841 if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
842 {
843 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
844 {
845 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
846 return FALSE;
847 }
848 }
849 else
850 {
851 VPU_MSG_INFO("%s MVD 3DTV sub\n",__FUNCTION__);
852 HAL_HVD_EX_PowerCtrl(TRUE);
853 }
854 }
855 else
856 {
857 VPU_MSG_ERR("(%d): do nothing, HVD already init\n", __LINE__);
858 }
859 }
860
861 //Check if we need to init HVD HW
862 #ifdef VDEC3
863 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
864 #else
865 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
866 #endif
867 {
868 if (!HAL_VPU_EX_MVDInUsed())
869 {
870 if (!HAL_MVD_InitHW())
871 {
872 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
873 return FALSE;
874 }
875 }
876
877 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
878 {
879 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
880 return FALSE;
881 }
882 }
883
884 #if SUPPORT_G2VP9 && defined(VDEC3)
885 if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
886 {
887 if (!HAL_VPU_EX_MVDInUsed())
888 {
889 if (!HAL_MVD_InitHW())
890 {
891 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
892 return FALSE;
893 }
894 }
895 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
896 {
897 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed for VP9\n", __LINE__);
898 return FALSE;
899 }
900 }
901 #endif
902
903 return TRUE;
904 }
905
_VPU_EX_InClock(MS_U32 u32type)906 static MS_U32 _VPU_EX_InClock(MS_U32 u32type)
907 {
908 switch (u32type)
909 {
910 case VPU_CLOCK_240MHZ:
911 return 240000000UL;
912 case VPU_CLOCK_216MHZ:
913 return 216000000UL;
914 case VPU_CLOCK_192MHZ:
915 return 192000000UL;
916 case VPU_CLOCK_320MHZ:
917 return 320000000UL;
918 case VPU_CLOCK_288MHZ:
919 return 288000000UL;
920 default:
921 return 240000000UL;
922 }
923 }
924
925
926 #if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_LINUX_KERNEL)
927 //For REE
HAL_VPU_EX_REE_RegisterMBX(void)928 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void)
929 {
930 //#ifndef MSOS_TYPE_LINUX_KERNEL
931 #if 1
932 MS_U8 ClassNum = 0;
933 MBX_Result result;
934
935 #if 0
936 if (bVPUMbxInitFlag == TRUE)
937 {
938 return TRUE;
939 }
940 #endif //201170110
941
942 if (E_MBX_SUCCESS != MApi_MBX_Init(E_MBX_CPU_MIPS,E_MBX_ROLE_HK,1000))
943 {
944 VPU_MSG_ERR("VDEC_TEE MApi_MBX_Init fail\n");
945 return FALSE;
946 }
947 else
948 {
949 MApi_MBX_Enable(TRUE);
950 }
951
952 result = MApi_MBX_QueryDynamicClass(E_MBX_CPU_MIPS_VPE1, "VDEC_TEE", (MS_U8 *)&ClassNum);
953
954 if (E_MBX_SUCCESS != result)
955 {
956 VPU_MSG_ERR("VDEC_TEE MApi_MBX_QueryDynamicClass fail,result %d\n",(unsigned int)result);
957 return FALSE;
958 }
959
960 result = MApi_MBX_RegisterMSG(ClassNum, 10);
961
962 if (( E_MBX_SUCCESS != result) && ( E_MBX_ERR_SLOT_AREADY_OPENNED != result ))
963 {
964 VPU_MSG_ERR("%s fail\n",__FUNCTION__);
965 return FALSE;
966 }
967 else
968 {
969 bVPUMbxInitFlag = TRUE;
970 u8VPUMbxMsgClass = ClassNum;
971 return TRUE;
972 }
973 #else
974 return FALSE;
975 #endif
976 }
_VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)977 VDEC_TEE_TO_REE_MBX_ACK_TYPE _VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)
978 {
979 MBX_Result result;
980 VDEC_TEE_TO_REE_MBX_ACK_TYPE u8Index;
981
982 if (pVPUHalContext->bEnableVPUSecureMode == FALSE)
983 {
984 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE;
985 }
986
987 if (bVPUMbxInitFlag == FALSE)
988 {
989 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID;
990 }
991
992 VPUReeToTeeMbxMsg.eRoleID = E_MBX_CPU_MIPS_VPE1;
993 VPUReeToTeeMbxMsg.u8Ctrl = 0;
994 VPUReeToTeeMbxMsg.eMsgType = E_MBX_MSG_TYPE_INSTANT;
995 VPUReeToTeeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
996 VPUReeToTeeMbxMsg.u8Index = msg_type;
997
998 result = MApi_MBX_SendMsg(&VPUReeToTeeMbxMsg);
999 if (E_MBX_SUCCESS != result)
1000 {
1001 printf("VDEC_TEE Send MBX fail,result %d\n",(unsigned int)result);
1002 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1003 }
1004
1005 // Receive Reply ACK from TEE side.
1006 memset(&VPUTeeToReeMbxMsg, 0, sizeof(MBX_Msg));
1007
1008 VPUTeeToReeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1009
1010 #if 0 // marked temperarily, wait kernel team to fix MApi_MBX_RecvMsg.
1011 if(E_MBX_SUCCESS != MApi_MBX_RecvMsg(TEE_MBX_MSG_CLASS, &(TEE_TO_REE_MBX_MSG), 20, MBX_CHECK_INSTANT_MSG))
1012 {
1013 VPU_MSG_ERR("VDEC get Secure world ACK fail\n");
1014 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1015 }
1016 else
1017 #else
1018 do
1019 {
1020 result = MApi_MBX_RecvMsg(u8VPUMbxMsgClass, &VPUTeeToReeMbxMsg, 2000, MBX_CHECK_INSTANT_MSG);
1021 } while(E_MBX_SUCCESS != result);
1022 #endif
1023 {
1024 u8Index = VPUTeeToReeMbxMsg.u8Index;
1025 VPU_MSG_DBG("VDEC get ACK cmd:%x\n", u8Index);
1026
1027 if (E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL == u8Index)
1028 {
1029 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1030 }
1031 }
1032
1033 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS;
1034 }
1035
HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)1036 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)
1037 {
1038 if(U32Type == SYS_TEEINFO_OSTYPE_NUTTX)
1039 {
1040 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1041 {
1042 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1043 return FALSE;
1044 }
1045 else
1046 {
1047 MS_VIRT u32VPUSHMoffset = (VPUTeeToReeMbxMsg.u8Parameters[0]&0xff) |
1048 ((VPUTeeToReeMbxMsg.u8Parameters[1]<<8)&0xff00)|
1049 ((VPUTeeToReeMbxMsg.u8Parameters[2]<<16)&0xff0000)|
1050 ((VPUTeeToReeMbxMsg.u8Parameters[3]<<24)&0xff000000);
1051 MS_U32 u32VPUSHMsize = (VPUTeeToReeMbxMsg.u8Parameters[4]&0xff) |
1052 ((VPUTeeToReeMbxMsg.u8Parameters[5]<<8)&0xff00)|
1053 ((VPUTeeToReeMbxMsg.u8Parameters[6]<<16)&0xff0000)|
1054 ((VPUTeeToReeMbxMsg.u8Parameters[7]<<24)&0xff000000);
1055
1056 VPU_MSG_INFO("u32VPUSHMoffset %lx,u32VPUSHMsize %x,miu %d\n",(unsigned long)u32VPUSHMoffset,(unsigned int)u32VPUSHMsize,VPUTeeToReeMbxMsg.u8Parameters[8]);
1057
1058
1059 MS_U32 u32Start;
1060
1061 if(VPUTeeToReeMbxMsg.u8Parameters[8] == 1)
1062 {
1063 _miu_offset_to_phy(E_CHIP_MIU_1, u32VPUSHMoffset, u32Start);
1064 pVPUHalContext->u32VPUSHMAddr = u32Start;
1065 }
1066 else if(VPUTeeToReeMbxMsg.u8Parameters[8] == 2)
1067 {
1068 _miu_offset_to_phy(E_CHIP_MIU_2, u32VPUSHMoffset, u32Start);
1069 pVPUHalContext->u32VPUSHMAddr = u32Start;
1070
1071 }
1072 else // == 0
1073 {
1074 pVPUHalContext->u32VPUSHMAddr = u32VPUSHMoffset;
1075 }
1076 }
1077 }
1078
1079 return TRUE;
1080 }
1081
HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)1082 MS_BOOL HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)
1083 {
1084 bVPUMbxInitFlag = TRUE;
1085 u8VPUMbxMsgClass = u8APIMbxMsgClass;
1086 return TRUE;
1087 }
1088
1089 #endif
1090
HAL_VPU_EX_GetFWReload(void)1091 MS_BOOL HAL_VPU_EX_GetFWReload(void)
1092 {
1093 return pVPUHalContext->bVpuExReloadFW;
1094 }
1095
_VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)1096 static MS_BOOL _VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)
1097 {
1098 if(*((MS_U8*)(u32SrcAddr))=='V' && *((MS_U8*)(u32SrcAddr+1))=='D'
1099 && *((MS_U8*)(u32SrcAddr+2))=='E' && *((MS_U8*)(u32SrcAddr+3))=='C'
1100 && *((MS_U8*)(u32SrcAddr+4))=='3' && *((MS_U8*)(u32SrcAddr+5))=='1'
1101 && *((MS_U8*)(u32SrcAddr+0xe8))=='V' && *((MS_U8*)(u32SrcAddr+0xe9))=='D'
1102 && *((MS_U8*)(u32SrcAddr+0xea))=='E' && *((MS_U8*)(u32SrcAddr+0xeb))=='C'
1103 && *((MS_U8*)(u32SrcAddr+0xec))=='3' && *((MS_U8*)(u32SrcAddr+0xed))=='0'
1104 )
1105 {
1106 return FALSE;
1107 }
1108 else
1109 {
1110 return TRUE;
1111 }
1112 }
1113
_VPU_EX_InitAll(VPU_EX_NDecInitPara * pInitPara)1114 static MS_BOOL _VPU_EX_InitAll(VPU_EX_NDecInitPara *pInitPara)
1115 {
1116 MS_PHY u32fwPA = NULL; //physical address
1117 VPU_EX_ClockSpeed eClkSpeed = E_VPU_EX_CLOCK_320MHZ;
1118
1119 if (TRUE == HAL_VPU_EX_IsPowered())
1120 {
1121 VPU_MSG_DBG("IsPowered\n");
1122 return TRUE;
1123 }
1124 else
1125 {
1126 //VPU hold
1127 HAL_VPU_EX_SwRst(FALSE);
1128
1129 //VPU clock on
1130 VPU_EX_InitParam VPUInitParams = {eClkSpeed, FALSE, -1, VPU_DEFAULT_MUTEX_TIMEOUT, TRUE};
1131
1132 if (VPU_I_R_ON_MIU1)
1133 VPUInitParams.u8MiuSel = 1;
1134 else
1135 VPUInitParams.u8MiuSel = 0;
1136 //else if (VPU_I_R_ON_MIU2)
1137 // VPUInitParams.u8MiuSel = 2;
1138
1139 HAL_VPU_EX_Init(&VPUInitParams);
1140 }
1141
1142 VPU_EX_FWCodeCfg *pFWCodeCfg = NULL;
1143 VPU_EX_TaskInfo *pTaskInfo = NULL;
1144 VPU_EX_VLCTblCfg *pVlcCfg = NULL;
1145
1146 if (pInitPara)
1147 {
1148 pFWCodeCfg = pInitPara->pFWCodeCfg;
1149 pTaskInfo = pInitPara->pTaskInfo;
1150 pVlcCfg = pInitPara->pVLCCfg;
1151 }
1152 else
1153 {
1154 VPU_MSG_DBG("(%d) NULL para\n", __LINE__);
1155 return FALSE;
1156 }
1157
1158 u32fwPA = MsOS_VA2PA(pFWCodeCfg->u32DstAddr);
1159 #if (defined(MSOS_TYPE_LINUX)||defined(MSOS_TYPE_LINUX_KERNEL))
1160 if(pVPUHalContext->bEnableVPUSecureMode == TRUE)
1161 {
1162 VPU_MSG_INFO("Load VDEC f/w code in Secure World\n");
1163
1164 if (FALSE == HAL_VPU_EX_GetFWReload())
1165 {
1166 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
1167 {
1168 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
1169 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1170 {
1171 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1172 return FALSE;
1173 }
1174 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1175 }
1176 else
1177 {
1178 //Check f/w prefix "VDEC30"
1179 if (_VPU_EX_IsNeedDecompress(pFWCodeCfg->u32DstAddr) != FALSE)
1180 {
1181 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
1182 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1183 {
1184 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1185 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1186 return FALSE;
1187 }
1188 }
1189 else
1190 {
1191 VPU_MSG_INFO("Skip loading fw this time!!!\n");
1192 }
1193 }
1194 }
1195 else
1196 {
1197 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1198 {
1199 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1200 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1201 return FALSE;
1202 }
1203 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1204 }
1205 }
1206 else
1207 #endif
1208 {
1209 VPU_MSG_INFO("Load VDEC f/w code in Normal World\n");
1210
1211 if (!HAL_VPU_EX_LoadCode(pFWCodeCfg))
1212 {
1213 VPU_MSG_ERR("HAL_VPU_EX_LoadCode fail!\n");
1214 return FALSE;
1215 }
1216 }
1217
1218 if (pVlcCfg)
1219 {
1220 if (!_VPU_EX_LoadVLCTable(pVlcCfg, pFWCodeCfg->u8SrcType))
1221 {
1222 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1223 return FALSE;
1224 }
1225 }
1226
1227 if (!HAL_VPU_EX_CPUSetting(u32fwPA))
1228 {
1229 VPU_MSG_ERR("HAL_VPU_EX_CPUSetting fail!\n");
1230 return FALSE;
1231 }
1232
1233 //Init HW
1234 if (FALSE == _VPU_EX_InitHW(pTaskInfo))
1235 {
1236 VPU_MSG_ERR("(%d): InitHW failed\n", __LINE__);
1237 //_MVD_INIT_FAIL_RET();
1238 return FALSE;
1239 }
1240 else
1241 {
1242 VPU_MSG_DBG("(%d): InitHW success\n", __LINE__);
1243 }
1244
1245 //set vpu clock to FW
1246 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1247 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1248
1249 ctl_ptr->statue = CTL_STU_NONE;
1250 //notify controller the interface version of VPU driver.
1251 ctl_ptr->ctl_interface = VPU_CTL_INTERFACE_VER;
1252 ctl_ptr->vpu_clk = _VPU_EX_InClock(eClkSpeed);
1253 MsOS_FlushMemory();
1254 VPU_MSG_DBG("clock speed=0x%x\n", ctl_ptr->vpu_clk);
1255
1256 //Release VPU: For dual decoder, we only release VPU if it is not released yet.
1257 if (TRUE == HAL_VPU_EX_IsRsted())
1258 {
1259 VPU_MSG_DBG("VPU_IsRsted\n");
1260 return TRUE;
1261 }
1262 else
1263 {
1264 HAL_VPU_EX_SwRstRelse();
1265 }
1266
1267 return TRUE;
1268 }
1269
_VPU_EX_DeinitHW(void)1270 static MS_BOOL _VPU_EX_DeinitHW(void)
1271 {
1272 MS_BOOL bRet = FALSE;
1273
1274 if (FALSE == HAL_VPU_EX_MVDInUsed())
1275 {
1276 bRet = HAL_MVD_DeinitHW();
1277 }
1278
1279 if (FALSE == HAL_VPU_EX_HVDInUsed())
1280 {
1281 bRet = HAL_HVD_EX_DeinitHW();
1282 }
1283 #if SUPPORT_G2VP9 && defined(VDEC3)
1284 if (FALSE == HAL_VPU_EX_G2VP9InUsed())
1285 {
1286 bRet = HAL_VP9_EX_DeinitHW();
1287 }
1288 #endif
1289 return bRet;
1290 }
1291
_VPU_EX_DeinitAll(void)1292 static MS_BOOL _VPU_EX_DeinitAll(void)
1293 {
1294 HAL_VPU_EX_SwRst(TRUE);
1295 _VPU_EX_DeinitHW();
1296 HAL_VPU_EX_DeInit();
1297
1298 return TRUE;
1299 }
1300
_VPU_EX_GetActiveCodecCnt(void)1301 static MS_U8 _VPU_EX_GetActiveCodecCnt(void)
1302 {
1303 MS_U32 i;
1304 MS_U8 u8ActiveCnt = 0;
1305 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
1306 {
1307 if (E_VPU_EX_DECODER_NONE != pVPUHalContext->_stVPUStream[i].eDecodertype)
1308 {
1309 u8ActiveCnt++;
1310 }
1311 }
1312 if (pVPUHalContext->u8TaskCnt != u8ActiveCnt)
1313 {
1314 VPU_MSG_ERR("Err u8TaskCnt(%d) != u8ActiveCnt(%d)\n", pVPUHalContext->u8TaskCnt, u8ActiveCnt);
1315 }
1316 VPU_MSG_DBG(" = %d\n", u8ActiveCnt);
1317 return u8ActiveCnt;
1318 }
_VPU_EX_ClockInv(MS_BOOL bEnable)1319 static void _VPU_EX_ClockInv(MS_BOOL bEnable)
1320 {
1321 if (TRUE)
1322 {
1323 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV);
1324 }
1325 else
1326 {
1327 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV);
1328 }
1329 }
1330
_VPU_EX_ClockSpeed(MS_U32 u32type)1331 static void _VPU_EX_ClockSpeed(MS_U32 u32type)
1332 {
1333 switch (u32type)
1334 {
1335 case VPU_CLOCK_240MHZ:
1336 case VPU_CLOCK_216MHZ:
1337 case VPU_CLOCK_192MHZ:
1338 case VPU_CLOCK_320MHZ:
1339 case VPU_CLOCK_288MHZ:
1340 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK);
1341 break;
1342 default:
1343 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_240MHZ, TOP_CKG_VPU_CLK_MASK);
1344 break;
1345 }
1346 }
1347
_VPU_EX_MAU_IDLE(void)1348 static MS_BOOL _VPU_EX_MAU_IDLE(void)
1349 {
1350 if (((_VPU_Read2Byte(MAU1_ARB0_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE)
1351 && ((_VPU_Read2Byte(MAU1_ARB1_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE))
1352 {
1353 return TRUE;
1354 }
1355 return FALSE;
1356 }
1357
1358
1359 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
_VPU_EX_DecompressBin(MS_VIRT u32SrcAddr,MS_U32 u32SrcSize,MS_VIRT u32DestAddr,MS_VIRT u32SlidingAddr)1360 static MS_BOOL _VPU_EX_DecompressBin(MS_VIRT u32SrcAddr, MS_U32 u32SrcSize, MS_VIRT u32DestAddr, MS_VIRT u32SlidingAddr)
1361 {
1362 if(_VPU_EX_IsNeedDecompress(u32SrcAddr))
1363 {
1364 ms_VDECDecompressInit((MS_U8*)u32SlidingAddr, (MS_U8*)u32DestAddr);
1365 ms_VDECDecompress((MS_U8*)u32SrcAddr, u32SrcSize);
1366 ms_VDECDecompressDeInit();
1367 return TRUE;
1368 }
1369 else
1370 {
1371 return FALSE;
1372 }
1373 }
1374 #endif
1375
HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)1376 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)
1377 {
1378 MS_BOOL bRet = TRUE;
1379 pVPUHalContext->_bVPUSingleMode = bEnable;
1380 return bRet;
1381 }
1382
HAL_VPU_EX_SetSTCMode(MS_U32 u32Id,MS_U32 u32STCIndex)1383 MS_BOOL HAL_VPU_EX_SetSTCMode(MS_U32 u32Id, MS_U32 u32STCIndex)
1384 {
1385 MS_BOOL bRet = TRUE;
1386 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1387 pVPUHalContext->_stVPUSTCMode[u8OffsetIdx].bSTCSetMode = TRUE;
1388 pVPUHalContext->_stVPUSTCMode[u8OffsetIdx].u32STCIndex = u32STCIndex;
1389
1390 return bRet;
1391 }
1392
HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg * pstCfg)1393 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg)
1394 {
1395 MS_BOOL bRet = TRUE;
1396 MS_U8 i=0;
1397 if (pstCfg != NULL)
1398 {
1399 pVPUHalContext->_stVPUDecMode.u8DecMod = pstCfg->u8DecMod;
1400 pVPUHalContext->_stVPUDecMode.u8CodecCnt = pstCfg->u8CodecCnt;
1401 for (i=0; ((i<pstCfg->u8CodecCnt)&&(i<VPU_MAX_DEC_NUM)); i++)
1402 {
1403 pVPUHalContext->_stVPUDecMode.u8CodecType[i] = pstCfg->u8CodecType[i];
1404 }
1405 pVPUHalContext->_stVPUDecMode.u8ArgSize = pstCfg->u8ArgSize;
1406 pVPUHalContext->_stVPUDecMode.u32Arg = pstCfg->u32Arg;
1407 }
1408 else
1409 {
1410 bRet = FALSE;
1411 }
1412 return bRet;
1413 }
1414
1415 //static MS_BOOL bVpuExReloadFW = TRUE;
1416 //static MS_BOOL bVpuExLoadFWRlt = FALSE;
HAL_VPU_EX_SetFWReload(MS_BOOL bReload)1417 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload)
1418 {
1419 pVPUHalContext->bVpuExReloadFW = bReload;
1420 //printf("%s bVpuExReloadFW = %x\n", __FUNCTION__, bVpuExReloadFW);
1421 return TRUE;
1422 }
1423
1424
1425 //-------------------------------------------------------------------------------------------------
1426 // Global Functions
1427 //-------------------------------------------------------------------------------------------------
1428 #ifdef VDEC3_FB
HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)1429 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
1430 {
1431 #if HVD_ENABLE_RV_FEATURE
1432 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
1433 {
1434 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
1435 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
1436 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1437
1438 if (pVlcCfg->u32BinSize)
1439 {
1440 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
1441
1442 if (HAL_MIU1_BASE <= MsOS_VA2PA(pVlcCfg->u32DstAddr))
1443 {
1444 cpyflag = E_SPIDMA_DEV_MIU1;
1445 }
1446 else
1447 {
1448 cpyflag = E_SPIDMA_DEV_MIU0;
1449 }
1450
1451 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
1452 {
1453 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
1454 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
1455
1456 return FALSE;
1457 }
1458 }
1459 else
1460 {
1461 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
1462 return FALSE;
1463 }
1464 #else
1465 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
1466 return FALSE;
1467 #endif
1468 }
1469 else
1470 {
1471 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
1472 {
1473 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
1474 {
1475 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
1476 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
1477
1478 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
1479 BDMA_Result bdmaRlt;
1480
1481 MsOS_FlushMemory();
1482 bdmaRlt = HVD_dmacpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1483
1484 if (E_BDMA_OK != bdmaRlt)
1485 {
1486 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
1487 }
1488 #else
1489 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1490 #endif
1491 }
1492 else
1493 {
1494 VPU_MSG_ERR
1495 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
1496 return FALSE;
1497 }
1498 }
1499 else
1500 {
1501 #if VPU_ENABLE_EMBEDDED_FW_BINARY
1502 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
1503 MS_U8 *pu8HVD_VLC_Binary;
1504
1505 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
1506
1507 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
1508 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long) pu8HVD_VLC_Binary),
1509 (MS_U32) sizeof(u8HVD_VLC_Binary));
1510
1511 HVD_memcpy((void *) (pVlcCfg->u32DstAddr),
1512 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1513 #else
1514 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
1515 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long) u8HVD_VLC_Binary,
1516 (MS_U32) sizeof(u8HVD_VLC_Binary));
1517
1518 HVD_memcpy(pVlcCfg->u32DstAddr, ((MS_VIRT) u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1519 #endif
1520 #else
1521 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
1522 return FALSE;
1523 #endif
1524 }
1525 }
1526 #endif
1527
1528 return TRUE;
1529 }
1530 #endif
1531 #ifdef VDEC3
HAL_VPU_EX_TaskCreate(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara,MS_BOOL bFWdecideFB,MS_U32 u32BBUId)1532 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId)
1533 #else
1534 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1535 #endif
1536 {
1537 VPU_EX_TaskInfo *pTaskInfo = pInitPara->pTaskInfo;
1538 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
1539 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
1540 VPU_EX_DecoderType eDecType = E_VPU_EX_DECODER_NONE;
1541 MS_U32 u32Arg = 0xFFFFFFFF;
1542 MS_U32 u32Timeout = 0;
1543 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
1544 MS_U32 u32CmdArg = 0;
1545 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1546 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1547
1548 _HAL_VPU_Entry();
1549 //Check FW buffer size
1550 if (1 == u8Offset)
1551 {
1552 MS_VIRT u32MinFWBuffSize = (u8Offset + 1) * VPU_FW_MEM_OFFSET;
1553 MS_VIRT u32CurFWBuffSize = pInitPara->pFWCodeCfg->u32DstSize;
1554
1555 if (u32CurFWBuffSize < u32MinFWBuffSize)
1556 {
1557 VPU_MSG_ERR("FW BuffSize(0x%lx < 0x%lx) is too small!\n", (unsigned long)u32CurFWBuffSize, (unsigned long)u32MinFWBuffSize);
1558 _HAL_VPU_Release();
1559 return FALSE;
1560 }
1561 }
1562
1563 if(( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id))
1564 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype)
1565 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
1566 {
1567 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
1568 }
1569 #ifdef VDEC3
1570 pVPUHalContext->u32FWCodeAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1571 #endif
1572
1573 if (0 == pVPUHalContext->u8TaskCnt)
1574 {
1575 //No task is created, need to load f/w, etc.
1576 VPU_MSG_DBG("u8TaskCnt=%d\n", pVPUHalContext->u8TaskCnt);
1577
1578 if (!_VPU_EX_InitAll(pInitPara))
1579 {
1580 VPU_MSG_DBG("(%d) fail to InitAll\n", __LINE__);
1581 _HAL_VPU_Release();
1582 return FALSE;
1583 }
1584
1585 //Check if controller finish initialization: clear mailbox, etc.
1586 //Need to check it before sending any controller commands!
1587 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1588 while (CTL_STU_NONE == ctl_ptr->statue)
1589 {
1590 if (HVD_GetSysTime_ms() > u32Timeout)
1591 {
1592 VPU_MSG_ERR("Ctl init timeout, st=%x\n", ctl_ptr->statue);
1593 VPU_MSG_ERR("version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1594 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1595 MS_U32 t=0;
1596 for (t=0; t<30; t++)
1597 {
1598 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
1599 }
1600 _HAL_VPU_Release();
1601 return FALSE;
1602 }
1603
1604 MsOS_ReadMemory();
1605 }
1606
1607 VPU_MSG_INFO("ctl_init_done: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1608 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1609
1610 }
1611 else
1612 {
1613 if (pVPUHalContext->_bVPUSingleMode)
1614 {
1615 //Show error message
1616 printf("This task will use dram instead of sram!!!\n");
1617 VPU_MSG_INFO("VDEC warn: this task will use dram instead of sram!!!\n");
1618 }
1619
1620 if (!_VPU_EX_InitHW(pInitPara->pTaskInfo))
1621 {
1622 VPU_MSG_DBG("(%d) fail to InitHW\n", __LINE__);
1623 _HAL_VPU_Release();
1624 return FALSE;
1625 }
1626 if (pInitPara->pVLCCfg)
1627 {
1628 if (!_VPU_EX_LoadVLCTable(pInitPara->pVLCCfg, pInitPara->pFWCodeCfg->u8SrcType))
1629 {
1630 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1631 _HAL_VPU_Release();
1632 return FALSE;
1633 }
1634 }
1635 }
1636
1637
1638 #ifdef VDEC3
1639 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1640 {
1641 MS_U64 max_addr_check = (sizeof(MS_PHY) == 4)?0xffffffff:0xffffffffffffffff;
1642 MS_PHY phy_dst_addr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1643 MS_PHY phy_multidecode_offset = u8Offset*VPU_FW_MEM_OFFSET;
1644 if(max_addr_check - phy_dst_addr > phy_multidecode_offset)
1645 {
1646 if(max_addr_check - phy_dst_addr - phy_multidecode_offset > VBBU_TABLE_START)
1647 {
1648 MS_PHY phy_addr = phy_dst_addr + VBBU_TABLE_START + phy_multidecode_offset;
1649 VDEC_VBBU *pTemp4 = (VDEC_VBBU *)MsOS_PA2KSEG1(phy_addr);
1650 memset(pTemp4,0,sizeof(VDEC_VBBU));
1651 *((unsigned int*)(pTemp4->u8Reserved)) = phy_dst_addr-HAL_MIU1_BASE;
1652 }
1653
1654 if(max_addr_check - phy_dst_addr - phy_multidecode_offset > DISP_QUEUE_START)
1655 {
1656 MS_PHY phy_addr = phy_dst_addr + DISP_QUEUE_START + phy_multidecode_offset;
1657 DISPQ_IN_DRAM *pTemp = (DISPQ_IN_DRAM *)MsOS_PA2KSEG1(phy_addr);
1658 memset(pTemp,0,sizeof(DISPQ_IN_DRAM));
1659 }
1660
1661 if(max_addr_check - phy_dst_addr - phy_multidecode_offset > VCOMMANDQ_INFO_START)
1662 {
1663 MS_PHY phy_addr = phy_dst_addr + VCOMMANDQ_INFO_START + phy_multidecode_offset;
1664 CMD_QUEUE *pTemp2 = (CMD_QUEUE *)MsOS_PA2KSEG1(phy_addr);
1665 memset(pTemp2,0,sizeof(CMD_QUEUE));
1666 pTemp2->u32HVD_DISPCMDQ_DRAM_ST_ADDR = VDISP_COMMANDQ_START + phy_multidecode_offset;
1667 pTemp2->u32HVD_CMDQ_DRAM_ST_ADDR = VNORMAL_COMMANDQ_START + phy_multidecode_offset;
1668 }
1669
1670 if(max_addr_check - phy_dst_addr - phy_multidecode_offset > VDISP_COMMANDQ_START)
1671 {
1672 MS_PHY phy_addr = phy_dst_addr + VDISP_COMMANDQ_START + phy_multidecode_offset;
1673 unsigned char* pTemp3 = (unsigned char*)MsOS_PA2KSEG1(phy_addr);
1674 memset(pTemp3,0,0x2000);
1675 }
1676
1677 if(max_addr_check - phy_dst_addr - phy_multidecode_offset > OFFSET_BASE)
1678 {
1679 MS_PHY phy_addr = phy_dst_addr + OFFSET_BASE + phy_multidecode_offset;
1680 unsigned int* pVersion = (unsigned int*)MsOS_PA2KSEG1(phy_addr);
1681 memset((void*)pVersion,0,0x8);
1682 *pVersion = 1; //0:diu, 1:wb
1683 }
1684 }
1685 }
1686
1687 #endif
1688
1689 #if 1 // For TEE
1690 #ifdef VDEC3
1691 #if SUPPORT_G2VP9
1692 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType ||
1693 E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1694 #else
1695 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1696 #endif
1697 #else
1698 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1699 #endif
1700 {
1701 MS_VIRT u32FWPhyAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1702
1703 if (pVPUHalContext->u32FWShareInfoAddr[u8Offset] == 0xFFFFFFFFUL)
1704 {
1705 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
1706 }
1707 else
1708 {
1709 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = pVPUHalContext->u32FWShareInfoAddr[u8Offset] - u32FWPhyAddr;
1710 }
1711
1712 MsOS_FlushMemory();
1713 VPU_MSG_DBG("task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1714
1715 ///printf("DRV side, share info offset = 0x%lx\n", pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
1716 ///printf("FW side, task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1717 }
1718 #endif
1719
1720 if ((pVPUHalContext->bEnableDymanicFBMode == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
1721 {
1722 ctl_ptr->FB_ADDRESS = pVPUHalContext->u32DynamicFBAddress;
1723 ctl_ptr->FB_Total_SIZE = pVPUHalContext->u32DynamicFBSize;
1724
1725 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_COMMON, 0);
1726
1727 MsOS_FlushMemory();
1728 }
1729
1730 if (pVPUHalContext->_stVPUSTCMode[u8Offset].bSTCSetMode)
1731 {
1732 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_STC_MODE, pVPUHalContext->_stVPUSTCMode[u8Offset].u32STCIndex);
1733 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1734 {
1735 VPU_MSG_ERR("E_HVD_CMD_STC_MODE NG eCtrlRet=%x\n", eCtrlRet);
1736 }
1737 }
1738
1739 if ((TRUE==pVPUHalContext->_bVPUSingleMode) || (E_VPU_DEC_MODE_SINGLE==pVPUHalContext->_stVPUDecMode.u8DecMod))
1740 {
1741 //Issue E_DUAL_CMD_SINGLE_TASK to FW controller
1742 //arg=1 to get better performance for single task
1743 u32CmdArg = (pVPUHalContext->_bVPUSingleMode) ? 1 : 0;
1744 VPU_MSG_DBG("Issue E_DUAL_CMD_SINGLE_TASK to FW controller arg=%x\n", u32CmdArg);
1745 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_SINGLE_TASK, u32CmdArg);
1746 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1747 {
1748 VPU_MSG_ERR("E_DUAL_CMD_SINGLE_TASK NG eCtrlRet=%x\n", eCtrlRet);
1749 }
1750 }
1751 else if (E_VPU_DEC_MODE_DUAL_3D==pVPUHalContext->_stVPUDecMode.u8DecMod)
1752 {
1753 if(pVPUHalContext->_stVPUDecMode.u8CodecType[0] != pVPUHalContext->_stVPUDecMode.u8CodecType[1])
1754 {
1755 switch (pVPUHalContext->_stVPUDecMode.u32Arg)
1756 {
1757 case E_VPU_CMD_MODE_KR3D_INTERLACE:
1758 u32CmdArg = CTL_MODE_3DTV;
1759 break;
1760 case E_VPU_CMD_MODE_KR3D_FORCE_P:
1761 u32CmdArg = CTL_MODE_3DTV_PROG;
1762 break;
1763 case E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH:
1764 u32CmdArg = CTL_MODE_3DTV_TWO_PITCH;
1765 break;
1766 case E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH:
1767 u32CmdArg = CTL_MODE_3DTV_PROG_TWO_PITCH;
1768 break;
1769 default:
1770 u32CmdArg = CTL_MODE_3DTV;
1771 VPU_MSG_INFO("%x not defined, use CTL_MODE_3DTV for KR3D\n", pVPUHalContext->_stVPUDecMode.u32Arg);
1772 break;
1773 }
1774 }
1775 else
1776 {
1777 u32CmdArg = CTL_MODE_3DWMV;
1778 }
1779 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1780 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1781 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1782 {
1783 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1784 }
1785 }
1786 else if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
1787 {
1788 if(E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC == pVPUHalContext->_stVPUDecMode.u32Arg)
1789 {
1790 u32CmdArg = CTL_MODE_ONE_STC;
1791 }
1792 else
1793 {
1794 u32CmdArg = (pVPUHalContext->_stVPUDecMode.u32Arg==E_VPU_CMD_MODE_PIP_SYNC_SWITCH) ? CTL_MODE_SWITCH_STC : CTL_MODE_NORMAL;
1795 }
1796 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1797 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1798 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1799 {
1800 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1801 }
1802 }
1803
1804 eCmd = _VPU_EX_MapCtrlCmd(pTaskInfo);
1805 #if defined(SUPPORT_NEW_MEM_LAYOUT)
1806 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1807 #ifdef VDEC3
1808 {
1809 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
1810 }
1811 #else
1812 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
1813 #endif
1814
1815 #ifdef VDEC3
1816 #if SUPPORT_G2VP9
1817 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1818 #else
1819 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1820 #endif
1821 {
1822 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + (u8Offset * VPU_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
1823 }
1824 #else
1825 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1826 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + HVD_SHARE_MEM_ST_OFFSET;
1827 #endif
1828 else
1829 {
1830 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
1831 _HAL_VPU_Release();
1832 return FALSE;
1833 }
1834 #else
1835 u32Arg = u8Offset * VPU_FW_MEM_OFFSET;
1836 #endif
1837
1838 VPRINTF("[NDec][%s][%d] create task : id 0x%x, cmd 0x%x, arg 0x%x, bbuID %d, offset %d \n", __FUNCTION__, __LINE__, u32Id, eCmd, u32Arg, u32BBUId, u8Offset);
1839 HAL_HVD_EX_SetCmd(u32Id, eCmd, u32Arg);
1840
1841 MsOS_ReadMemory();
1842 VPU_MSG_INFO("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1843 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1844
1845 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1846 while (CTL_TASK_CMDRDY != ctl_ptr->task_statue[u8Offset])
1847 {
1848 if (HVD_GetSysTime_ms() > u32Timeout)
1849 {
1850 VPU_MSG_ERR("Task %d creation timeout\n", u8Offset);
1851 MS_U32 t=0;
1852 for (t=0; t<30; t++)
1853 {
1854 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
1855 }
1856 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1857 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
1858 VPU_MSG_ERR("set bVpuExLoadFWRlt as FALSE\n\n");
1859 _HAL_VPU_Release();
1860 return FALSE;
1861 //#endif
1862 }
1863
1864 MsOS_ReadMemory();
1865 }
1866
1867 VPU_MSG_INFO("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1868 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1869
1870 #ifdef VDEC3
1871 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1872 #else
1873 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1874 #endif
1875 {
1876 HAL_HVD_EX_SetNalTblAddr(u32Id);
1877 }
1878
1879 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1880 {
1881 eDecType = E_VPU_EX_DECODER_MVD;
1882 }
1883 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1884 {
1885 eDecType = E_VPU_EX_DECODER_HVD;
1886 }
1887 #ifdef VDEC3
1888 else if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1889 {
1890 eDecType = E_VPU_EX_DECODER_EVD;
1891 }
1892 #if SUPPORT_G2VP9
1893 else if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1894 {
1895 eDecType = E_VPU_EX_DECODER_G2VP9;
1896 }
1897 #endif
1898 #endif
1899 else
1900 {
1901 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
1902 _HAL_VPU_Release();
1903 return FALSE;
1904 }
1905
1906 #ifdef VDEC3
1907 if ((bFWdecideFB == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
1908 {
1909 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBADDR, pInitPara->pFBCfg->u32FrameBufAddr);
1910 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBSIZE, pInitPara->pFBCfg->u32FrameBufSize);
1911 }
1912 #endif
1913
1914 if (pTaskInfo->eDecType != eDecType)
1915 {
1916 VPU_MSG_ERR("warning pTaskInfo->eDecType=%x not %x\n",
1917 pTaskInfo->eDecType, eDecType);
1918 }
1919 goto _SAVE_DEC_TYPE;
1920
1921 _SAVE_DEC_TYPE:
1922 if (pVPUHalContext->_stVPUStream[u8Offset].eStreamId == (u32Id & 0xFF))
1923 {
1924 pVPUHalContext->_stVPUStream[u8Offset].eDecodertype = eDecType;
1925 }
1926 else
1927 {
1928 VPU_MSG_ERR("Cannot save eDecType!!\n");
1929 }
1930
1931 (pVPUHalContext->u8TaskCnt)++;
1932 _HAL_VPU_Release();
1933 return TRUE;
1934 }
1935
HAL_VPU_EX_TaskDelete(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara)1936 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1937 {
1938 HVD_Return eRet;
1939 #ifdef VDEC3
1940 HVD_User_Cmd eCmd = E_NST_CMD_DEL_TASK;
1941 #else
1942 HVD_User_Cmd eCmd = E_DUAL_CMD_DEL_TASK;
1943 #endif
1944 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1945 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
1946
1947 _HAL_VPU_Entry();
1948 VPU_MSG_DBG("DecType=%d\n", pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype);
1949
1950 eRet = HAL_HVD_EX_SetCmd(u32Id, eCmd, u8OffsetIdx);
1951 if(eRet != E_HVD_RETURN_SUCCESS)
1952 {
1953 VPU_MSG_ERR("VPU fail to DEL Task %d\n", eRet);
1954 }
1955
1956 {
1957 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1958 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1959 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1960
1961 MsOS_ReadMemory();
1962
1963 VPU_MSG_DBG("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1964 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1965
1966 while (CTL_TASK_NONE != ctl_ptr->task_statue[u8OffsetIdx])
1967 {
1968 if (HVD_GetSysTime_ms() > u32Timeout)
1969 {
1970 VPU_MSG_ERR("Task %u deletion timeout\n", u8OffsetIdx);
1971 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
1972 VPU_MSG_ERR("Set bVpuExLoadFWRlt as FALSE\n");
1973
1974 if(pVPUHalContext->u8TaskCnt == 1)
1975 {
1976 VPU_MSG_ERR("Due to one task remain, driver can force delete task\n");
1977 break;
1978 }
1979 else if(pVPUHalContext->u8TaskCnt == 2)
1980 {
1981 VPU_MSG_ERR("Due to two tasks remain, driver can't force delete task\n");
1982 break;
1983 }
1984 else
1985 {
1986 VPU_MSG_ERR("Task number is not correct\n");
1987 _HAL_VPU_Release();
1988 return FALSE;
1989 }
1990 }
1991
1992 MsOS_ReadMemory();
1993 }
1994
1995 VPU_MSG_DBG("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1996 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1997 }
1998
1999 #if SUPPORT_EVD
2000 if (pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype == E_VPU_EX_DECODER_EVD)
2001 {
2002 HAL_EVD_EX_ClearTSPInput(u32Id);
2003 }
2004 #endif
2005
2006 pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype = E_VPU_EX_DECODER_NONE;
2007 if( (u8OffsetIdx == 0) && (pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId == E_HAL_VPU_MVC_MAIN_VIEW))
2008 {
2009 pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId = E_HAL_VPU_N_STREAM0;
2010 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2011 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2012 }
2013
2014 if (pVPUHalContext->u8TaskCnt)
2015 {
2016 (pVPUHalContext->u8TaskCnt)--;
2017 }
2018 else
2019 {
2020 VPU_MSG_DBG("Warning: u8TaskCnt=0\n");
2021 }
2022
2023 if (0 == pVPUHalContext->u8TaskCnt)
2024 {
2025 int i;
2026 VPU_MSG_DBG("u8TaskCnt=%d time to terminate\n", pVPUHalContext->u8TaskCnt);
2027 _VPU_EX_DeinitAll();
2028 HAL_VPU_EX_SetSingleDecodeMode(FALSE);
2029 pVPUHalContext->u32VPUSHMAddr = 0;
2030
2031 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
2032 {
2033 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
2034 }
2035 }
2036 else
2037 {
2038 pVPUHalContext->u32FWShareInfoAddr[u8OffsetIdx] = 0xFFFFFFFFUL;
2039 _VPU_EX_DeinitHW();
2040 }
2041
2042 _HAL_VPU_Release();
2043 return TRUE;
2044 }
2045
HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg * pFWCodeCfg)2046 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg)
2047 {
2048 MS_VIRT u32DestAddr = pFWCodeCfg->u32DstAddr;
2049 MS_VIRT u32BinAddr = pFWCodeCfg->u32BinAddr;
2050 MS_U32 u32Size = pFWCodeCfg->u32BinSize;
2051 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2052 MS_U32 u32DestSize = pFWCodeCfg->u32DstSize;
2053 #endif
2054
2055 if (FALSE == HAL_VPU_EX_GetFWReload())
2056 {
2057 //printf("%s bFWReload FALSE!!!\n", __FUNCTION__);
2058 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
2059 {
2060 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
2061 }
2062 else
2063 {
2064 //Check f/w prefix "VDEC30"
2065 if (_VPU_EX_IsNeedDecompress(u32DestAddr)!=FALSE)
2066 {
2067 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
2068 }
2069 else
2070 {
2071 VPU_MSG_INFO("Skip loading fw this time!!!\n");
2072 return TRUE;
2073 }
2074 }
2075 }
2076
2077 if (E_HVD_FW_INPUT_SOURCE_FLASH == pFWCodeCfg->u8SrcType)
2078 {
2079 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
2080 if (u32Size != 0)
2081 {
2082 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
2083
2084 if (HAL_MIU1_BASE <= MsOS_VA2PA(u32DestAddr))
2085 {
2086 cpyflag = E_SPIDMA_DEV_MIU1;
2087 }
2088 else
2089 {
2090 cpyflag = E_SPIDMA_DEV_MIU0;
2091 }
2092
2093 if (!HVD_FLASHcpy(MsOS_VA2PA(u32DestAddr), MsOS_VA2PA(u32BinAddr), u32Size, cpyflag))
2094 {
2095 goto _load_code_fail;
2096 }
2097 }
2098 else
2099 {
2100 goto _load_code_fail;
2101 }
2102 #else
2103 goto _load_code_fail;
2104 #endif
2105 }
2106 else if (E_HVD_FW_INPUT_SOURCE_DRAM == pFWCodeCfg->u8SrcType)
2107 {
2108 if (u32BinAddr != 0 && u32Size != 0)
2109 {
2110 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2111 if(_VPU_EX_DecompressBin(u32BinAddr, u32Size, u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2112 {
2113 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2114 {
2115 VPU_MSG_INFO("Decompress ok!!!\n");
2116 }
2117 else
2118 {
2119 VPU_MSG_INFO("Decompress fail!!!\n");
2120 }
2121 }
2122 else
2123 #endif
2124 {
2125 HVD_memcpy(u32DestAddr, u32BinAddr, u32Size);
2126 }
2127 }
2128 else
2129 {
2130 goto _load_code_fail;
2131 }
2132 }
2133 else
2134 {
2135 #if VPU_ENABLE_EMBEDDED_FW_BINARY
2136 VPU_MSG_INFO("Load FW inD2D: dest=0x%lx, source=0x%lx, size=%d\n",
2137 (unsigned long)u32DestAddr, ((unsigned long) u8HVD_FW_Binary),
2138 (MS_U32) sizeof(u8HVD_FW_Binary));
2139
2140 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2141 if(_VPU_EX_DecompressBin((MS_VIRT)u8HVD_FW_Binary, (MS_U32)sizeof(u8HVD_FW_Binary), u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2142 {
2143 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2144 {
2145 VPU_MSG_INFO("Decompress ok!!!\n");
2146 }
2147 else
2148 {
2149 VPU_MSG_INFO("Decompress fail!!!\n");
2150 }
2151 }
2152 else
2153 #endif
2154 {
2155 HVD_memcpy(u32DestAddr, (MS_VIRT)u8HVD_FW_Binary, sizeof(u8HVD_FW_Binary));
2156 }
2157 #else
2158 goto _load_code_fail;
2159 #endif
2160 }
2161
2162 MAsm_CPU_Sync();
2163 MsOS_FlushMemory();
2164
2165 if (FALSE == (*((MS_U8*)(u32DestAddr+6))=='R' && *((MS_U8*)(u32DestAddr+7))=='2'))
2166 {
2167 VPU_MSG_ERR("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(u32DestAddr+6), *(MS_U8*)(u32DestAddr+7));
2168 goto _load_code_fail;
2169 }
2170
2171 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
2172 return TRUE;
2173
2174 _load_code_fail:
2175 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
2176 return FALSE;
2177 }
2178
HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)2179 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)
2180 {
2181 u32VPURegOSBase = u32RegBase;
2182 }
2183
HAL_VPU_EX_Init_Share_Mem(void)2184 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void)
2185 {
2186 #if ((defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS)) && (!defined(SUPPORT_X_MODEL_FEATURE)))
2187
2188 MS_U32 u32ShmId;
2189 MS_VIRT u32Addr;
2190 MS_U32 u32BufSize;
2191
2192
2193 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HAL VPU",
2194 sizeof(VPU_Hal_CTX),
2195 &u32ShmId,
2196 &u32Addr,
2197 &u32BufSize,
2198 MSOS_SHM_QUERY))
2199 {
2200 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HAL VPU",
2201 sizeof(VPU_Hal_CTX),
2202 &u32ShmId,
2203 &u32Addr,
2204 &u32BufSize,
2205 MSOS_SHM_CREATE))
2206 {
2207 VPU_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
2208 if(pVPUHalContext == NULL)
2209 {
2210 pVPUHalContext = &gVPUHalContext;
2211 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2212 _VPU_EX_Context_Init();
2213 printf("[%s]Global structure init Success!!!\n",__FUNCTION__);
2214 }
2215 else
2216 {
2217 printf("[%s]Global structure exists!!!\n",__FUNCTION__);
2218 }
2219 //return FALSE;
2220 }
2221 else
2222 {
2223 memset((MS_U8*)u32Addr,0,sizeof(VPU_Hal_CTX));
2224 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for one process
2225 _VPU_EX_Context_Init();
2226 }
2227 }
2228 else
2229 {
2230 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for another process
2231 }
2232 #else
2233 if(pVPUHalContext == NULL)
2234 {
2235 pVPUHalContext = &gVPUHalContext;
2236 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2237 _VPU_EX_Context_Init();
2238 }
2239 #endif
2240
2241 return TRUE;
2242
2243 }
2244
HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)2245 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)
2246 {
2247 MS_U32 i = 0;
2248
2249 _HAL_VPU_MutexCreate();
2250
2251 _HAL_VPU_Entry();
2252
2253 if (E_HAL_VPU_MVC_STREAM == eStreamType)
2254 {
2255 if((E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype) && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
2256 {
2257 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
2258 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2259 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2260 _HAL_VPU_Release();
2261 return pVPUHalContext->_stVPUStream[0].eStreamId; /// Need to check
2262 }
2263 }
2264 else if (E_HAL_VPU_MAIN_STREAM == eStreamType)
2265 {
2266 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2267 {
2268 if ((E_HAL_VPU_MAIN_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2269 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2270 {
2271 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2272 _HAL_VPU_Release();
2273 return pVPUHalContext->_stVPUStream[i].eStreamId;
2274 }
2275 }
2276 }
2277 else if (E_HAL_VPU_SUB_STREAM == eStreamType)
2278 {
2279 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2280 {
2281 if ((E_HAL_VPU_SUB_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2282 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2283 {
2284 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2285 _HAL_VPU_Release();
2286 return pVPUHalContext->_stVPUStream[i].eStreamId;
2287 }
2288 }
2289 }
2290 #ifdef VDEC3
2291 else if (eStreamType >= E_HAL_VPU_N_STREAM && eStreamType < (E_HAL_VPU_N_STREAM + VPU_MAX_DEC_NUM))
2292 {
2293 #if 1 // bound FW task to main/sub stream
2294 i = eStreamType - E_HAL_VPU_N_STREAM;
2295 if (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_NONE)
2296 {
2297 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2298 _HAL_VPU_Release();
2299 return pVPUHalContext->_stVPUStream[i].eStreamId;
2300 }
2301 #else // dynamic select FW task id
2302 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2303 {
2304 if ((E_HAL_VPU_N_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2305 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2306 {
2307 return pVPUHalContext->_stVPUStream[i].eStreamId;
2308 }
2309 }
2310 #endif
2311 }
2312 #endif
2313
2314 _HAL_VPU_Release();
2315
2316 return E_HAL_VPU_STREAM_NONE;
2317 }
2318
HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)2319 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)
2320 {
2321 _HAL_VPU_Entry();
2322
2323 if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET_MVC)
2324 {
2325 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2326 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2327 }
2328 else if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET)
2329 {
2330 pVPUHalContext->_stVPUStream[u8Idx].eDecodertype = E_VPU_EX_DECODER_NONE;
2331 }
2332
2333 _HAL_VPU_Release();
2334
2335 return TRUE;
2336 }
2337
HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream)2338 MS_U8 HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream)
2339 {
2340 MS_U8 u8Idx = 0;
2341
2342 //VPRINTF("[NDec][%s][%d] eStream = %d\n", __FUNCTION__, __LINE__, eStream);
2343
2344 if(eStream == E_VPU_ORIGINAL_MAIN_STREAM)
2345 {
2346 if(pVPUHalContext->_stVPUStream[0].eDecodertype == E_VPU_EX_DECODER_NONE)
2347 {
2348 //VPRINTF("[NDec][%s][%d] main stream using u8Idx = 0\n", __FUNCTION__, __LINE__);
2349 return 0;
2350 }
2351 }
2352 else if(eStream == E_VPU_ORIGINAL_SUB_STREAM)
2353 {
2354 if(pVPUHalContext->_stVPUStream[1].eDecodertype == E_VPU_EX_DECODER_NONE)
2355 {
2356 //VPRINTF("[NDec][%s][%d] sub stream using u8Idx = 1\n", __FUNCTION__, __LINE__);
2357 return 1;
2358 }
2359 }
2360
2361 for (u8Idx = 0; u8Idx < MAX_SUPPORT_DECODER_NUM; u8Idx++)
2362 {
2363 if (pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_NONE)
2364 break;
2365 }
2366
2367 if (u8Idx >= MAX_SUPPORT_DECODER_NUM)
2368 {
2369 VPU_MSG_ERR("all vpu free streams are occupied \n");
2370 return 0xFF;
2371 }
2372
2373 VPU_MSG_DBG("available vpu free stream %d \n", u8Idx);
2374 return u8Idx;
2375 }
2376
HAL_VPU_EX_Init(VPU_EX_InitParam * InitParams)2377 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams)
2378 {
2379 VPU_MSG_DBG("Inv=%d, clk=%d\n", InitParams->bClockInv, InitParams->eClockSpeed);
2380
2381 // enable module
2382 _VPU_EX_ClockInv(InitParams->bClockInv);
2383 _VPU_EX_ClockSpeed(InitParams->eClockSpeed);
2384 HAL_VPU_EX_PowerCtrl(TRUE);
2385
2386 #if 1 //Create VPU's own mutex
2387 //_HAL_VPU_MutexCreate();
2388 #else
2389 pVPUHalContext->s32VPUMutexID = InitParams->s32VPUMutexID;
2390 pVPUHalContext->u32VPUMutexTimeOut = InitParams->u32VPUMutexTimeout;
2391 #endif
2392
2393 return TRUE;
2394 }
2395
HAL_VPU_EX_DeInit(void)2396 MS_BOOL HAL_VPU_EX_DeInit(void)
2397 {
2398 if (0 != _VPU_EX_GetActiveCodecCnt())
2399 {
2400 VPU_MSG_DBG("do nothing since codec is active.\n");
2401 return TRUE;
2402 }
2403
2404 memset(&(pVPUHalContext->_stVPUDecMode),0,sizeof(VPU_EX_DecModCfg));
2405
2406 HAL_VPU_EX_PowerCtrl(FALSE);
2407 HAL_VPU_EX_SwRelseMAU();
2408 //_HAL_VPU_MutexDelete();
2409
2410 return TRUE;
2411 }
2412
HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)2413 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)
2414 {
2415 if (bEnable)
2416 {
2417 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
2418 pVPUHalContext->_bVPUPowered = TRUE;
2419 }
2420 else
2421 {
2422 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS);
2423 pVPUHalContext->_bVPUPowered = FALSE;
2424 }
2425 }
2426
HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)2427 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)
2428 {
2429 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable);
2430 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable);
2431 _VPU_MIU_SetReqMask(VPU_I_R, bEnable);
2432 VPU_EX_TimerDelayMS(1);
2433 }
2434
2435 ///-----------------------------------------------------------------------------
2436 /// config AVCH264 CPU
2437 /// @param u32StAddr \b IN: CPU binary code base address in DRAM.
2438 /// @param u8dlend_en \b IN: endian
2439 /// - 1, little endian
2440 /// - 0, big endian
2441 ///-----------------------------------------------------------------------------
HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)2442 MS_BOOL HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)
2443 {
2444 MS_BOOL bRet = TRUE;
2445 MS_U32 u32Offset = 0;
2446 MS_U16 tempreg = 0;
2447
2448 u32Offset = (u32StAddr >= HAL_MIU1_BASE) ? (u32StAddr-HAL_MIU1_BASE) : u32StAddr ;
2449 _VPU_Write2Byte(VPU_REG_SPI_BASE, 0xC000);
2450 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT );
2451 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT );
2452 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_L, 0xc000);
2453 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_H, 0xffff);
2454 _VPU_Write2Byte(VPU_REG_IO1_BASE, 0xf900);
2455 _VPU_Write2Byte(VPU_REG_IO2_BASE, 0xf000);
2456 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_L, 0x0000);
2457 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_H, 0xf200);
2458
2459
2460 #ifdef ENABLE_EXTERNAL_DS_BUFFER
2461 //// Do not force MIU
2462 if(u32StAddr >= HAL_MIU1_BASE)
2463 {
2464 // Data sram base Unit: byte address
2465 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)((u32Offset | VPU_MIU1BASE_ADDR) & 0x0000ffff)) ;
2466 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)(((u32Offset | VPU_MIU1BASE_ADDR)>>16) & 0xffff));
2467 // Instruction sram base Unit: byte address
2468 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2469 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2470 }
2471 else
2472 {
2473 // Data sram base Unit: byte address
2474 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2475 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)((u32Offset>>16) & 0xffff));
2476 // Instruction sram base Unit: byte address
2477 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2478 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset>>16) & 0xffff));
2479 }
2480 #else
2481 if(u32StAddr >= HAL_MIU1_BASE)
2482 {
2483 // Data sram base Unit: byte address
2484 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2485 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2486 // Instruction sram base Unit: byte address
2487 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2488 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2489
2490 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8b00);
2491 }
2492 else
2493 {
2494 // Data sram base Unit: byte address
2495 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2496 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)((u32Offset>>16) & 0xffff));
2497 // Instruction sram base Unit: byte address
2498 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2499 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset>>16) & 0xffff));
2500
2501 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2502 }
2503 #endif
2504
2505 tempreg = _VPU_Read2Byte(VPU_REG_CONTROL_SET);
2506 tempreg |= VPU_REG_IO2_EN;
2507 tempreg |= VPU_REG_QMEM_SPACE_EN;
2508 _VPU_Write2Byte(VPU_REG_CONTROL_SET, tempreg);
2509
2510 return bRet;
2511 }
2512
2513 ///-----------------------------------------------------------------------------
2514 /// Set IQMem data access mode or instruction fetch mode
2515 /// @param u8dlend_en \b IN: endian
2516 /// - 1, switch to data access mode
2517 /// - 0, switch to instruction fetch mode
2518 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)2519 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)
2520 {
2521
2522 if(bEnable){
2523
2524 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)|0x10);
2525 _VPU_Write2Byte(VPU_REG_QMEM_OWNER, _VPU_Read2Byte(VPU_REG_QMEM_OWNER)&0xFFDE);
2526
2527 }
2528 else{
2529
2530 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)& 0xFFEF);
2531
2532 }
2533 }
2534
2535 ///-----------------------------------------------------------------------------
2536 /// H.264 SW reset
2537 /// @return TRUE or FALSE
2538 /// - TRUE, Success
2539 /// - FALSE, Failed
2540 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)2541 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2542 {
2543 MS_U16 tempreg = 0, tempreg1 = 0;
2544
2545 //From T4, need to check MAU idle before reset VPU
2546 if (bCheckMauIdle)
2547 {
2548 MS_U32 mau_idle_cnt = 100;// ms
2549 while (mau_idle_cnt)
2550 {
2551 if (TRUE == _VPU_EX_MAU_IDLE())
2552 {
2553 break;
2554 }
2555 mau_idle_cnt--;
2556 MsOS_DelayTask(1);
2557 }
2558
2559 if (mau_idle_cnt == 0)
2560 {
2561 printf("MAU idle time out~~~~~\n");
2562 }
2563 }
2564
2565
2566 HAL_VPU_EX_MIU_RW_Protect(TRUE);
2567
2568 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2569 tempreg1 |= MAU1_REG_SW_RESET;
2570 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2571
2572 #if defined(UDMA_FPGA_ENVI)
2573 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
2574 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
2575 #endif
2576
2577 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2578 tempreg &= ~VPU_REG_CPU_R2_EN;
2579 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2580 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2581 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2582
2583 VPU_EX_TimerDelayMS(1);
2584 HAL_VPU_EX_MIU_RW_Protect(FALSE);
2585
2586 pVPUHalContext->_bVPURsted = FALSE;
2587 return TRUE;
2588 }
2589
2590 ///-----------------------------------------------------------------------------
2591 /// CPU reset release
2592 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRstRelse(void)2593 void HAL_VPU_EX_SwRstRelse(void)
2594 {
2595 MS_U16 tempreg = 0, tempreg1 = 0;
2596
2597 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2598 tempreg |= VPU_REG_CPU_R2_EN;
2599 tempreg |= VPU_REG_CPU_SW_RSTZ;
2600 tempreg |= VPU_REG_CPU_MIU_SW_RSTZ;
2601 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2602
2603 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2604 tempreg1 &= ~MAU1_REG_SW_RESET;
2605 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2606
2607 pVPUHalContext->_bVPURsted = TRUE;
2608 }
2609
HAL_VPU_EX_SwRelseMAU(void)2610 void HAL_VPU_EX_SwRelseMAU(void)
2611 {
2612 MS_U16 tempreg = 0;
2613
2614 tempreg = _VPU_Read2Byte(MAU1_CPU_RST);
2615 tempreg &= ~MAU1_REG_SW_RESET;
2616 _VPU_Write2Byte(MAU1_CPU_RST, tempreg);
2617 }
2618
HAL_VPU_EX_MemRead(MS_VIRT u32Addr)2619 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Addr)
2620 {
2621 MS_U32 u32value = 0;
2622
2623 return u32value;
2624 }
2625
HAL_VPU_EX_MemWrite(MS_VIRT u32Addr,MS_U32 u32value)2626 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Addr, MS_U32 u32value)
2627 {
2628 MS_BOOL bRet = TRUE;
2629
2630 return bRet;
2631 }
2632
2633 ///-----------------------------------------------------------------------------
2634 /// Check AVCH264 Ready or not
2635 /// @return TRUE or FALSE
2636 /// - TRUE, MailBox is free
2637 /// - FALSE, MailBox is busy
2638 /// @param u8MBox \b IN: MailBox to check
2639 /// - AVCH264_HI_MBOX0,
2640 /// - AVCH264_HI_MBOX1,
2641 /// - AVCH264_RISC_MBOX0,
2642 /// - AVCH264_RISC_MBOX1,
2643 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRdy(MS_U32 u32type)2644 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type)
2645 {
2646 MS_BOOL bResult = FALSE;
2647
2648 switch (u32type)
2649 {
2650 case VPU_HI_MBOX0:
2651 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
2652 break;
2653 case VPU_HI_MBOX1:
2654 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
2655 break;
2656 case VPU_RISC_MBOX0:
2657 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
2658 break;
2659 case VPU_RISC_MBOX1:
2660 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
2661 break;
2662 default:
2663 break;
2664 }
2665 return bResult;
2666 }
2667
2668
2669 ///-----------------------------------------------------------------------------
2670 /// Read message from AVCH264
2671 /// @return TRUE or FALSE
2672 /// - TRUE, success
2673 /// - FALSE, failed
2674 /// @param u8MBox \b IN: MailBox to read
2675 /// - AVCH264_RISC_MBOX0
2676 /// - AVCH264_RISC_MBOX1
2677 /// @param u32Msg \b OUT: message read
2678 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRead(MS_U32 u32type,MS_U32 * u32Msg)2679 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 * u32Msg)
2680 {
2681 MS_BOOL bResult = TRUE;
2682
2683 switch (u32type)
2684 {
2685 case VPU_HI_MBOX0:
2686 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_H)) << 16) |
2687 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_L)));
2688 break;
2689 case VPU_HI_MBOX1:
2690 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_H)) << 16) |
2691 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_L)));
2692 break;
2693 case VPU_RISC_MBOX0:
2694 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_H)) << 16) |
2695 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_L)));
2696 break;
2697 case VPU_RISC_MBOX1:
2698 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_H)) << 16) |
2699 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_L)));
2700 break;
2701 default:
2702 *u32Msg = 0;
2703 bResult = FALSE;
2704 break;
2705 }
2706 return bResult;
2707 }
2708
2709 ///-----------------------------------------------------------------------------
2710 /// Mailbox from AVCH264 clear bit resest
2711 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxClear(MS_U32 u32type)2712 void HAL_VPU_EX_MBoxClear(MS_U32 u32type)
2713 {
2714 switch (u32type)
2715 {
2716 case VPU_RISC_MBOX0:
2717 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR);
2718 break;
2719 case VPU_RISC_MBOX1:
2720 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR);
2721 break;
2722 default:
2723 break;
2724 }
2725 }
2726
2727 ///-----------------------------------------------------------------------------
2728 /// Send message to AVCH264
2729 /// @return TRUE or FALSE
2730 /// - TRUE, Success
2731 /// - FALSE, Failed
2732 /// @param u8MBox \b IN: MailBox
2733 /// - AVCH264_HI_MBOX0,
2734 /// - AVCH264_HI_MBOX1,
2735 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxSend(MS_U32 u32type,MS_U32 u32Msg)2736 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg)
2737 {
2738 MS_BOOL bResult = TRUE;
2739
2740 VPU_MSG_DBG("type=%u, msg=0x%x\n", u32type, u32Msg);
2741
2742 switch (u32type)
2743 {
2744 case VPU_HI_MBOX0:
2745 {
2746 _VPU_Write4Byte(VPU_REG_HI_MBOX0_L, u32Msg);
2747 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX0_SET, VPU_REG_HI_MBOX0_SET);
2748 break;
2749 }
2750 case VPU_HI_MBOX1:
2751 {
2752 _VPU_Write4Byte(VPU_REG_HI_MBOX1_L, u32Msg);
2753 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX1_SET, VPU_REG_HI_MBOX1_SET);
2754 break;
2755 }
2756 default:
2757 {
2758 bResult = FALSE;
2759 break;
2760 }
2761 }
2762
2763 return bResult;
2764 }
2765
HAL_VPU_EX_GetProgCnt(void)2766 MS_U32 HAL_VPU_EX_GetProgCnt(void)
2767 {
2768
2769 MS_U16 expc_l=0;
2770 MS_U16 expc_h=0;
2771 expc_l = _VPU_Read2Byte(VPU_REG_EXPC_L) & 0xFFFF;
2772 expc_h = _VPU_Read2Byte(VPU_REG_EXPC_H) & 0xFFFF;
2773 return (((MS_U32)expc_h) << 16) | (MS_U32)expc_l;
2774 }
2775
HAL_VPU_EX_GetTaskId(MS_U32 u32Id)2776 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id)
2777 {
2778 return _VPU_EX_GetOffsetIdx(u32Id);
2779 }
2780
HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id,MS_VIRT u32ShmAddr)2781 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr)
2782 {
2783 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
2784
2785 if (u32ShmAddr == 0)
2786 {
2787 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
2788 }
2789 else
2790 {
2791 if (u8Offset == 0)
2792 {
2793 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr;
2794 }
2795 else if (u8Offset == 1)
2796 {
2797 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr + TEE_ONE_TASK_SHM_SIZE;
2798 }
2799 }
2800
2801 VPU_MSG_DBG("set PA ShareInfoAddr[%d] = 0x%lx \n", u8Offset, (unsigned long)pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
2802 return;
2803 }
2804
HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)2805 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)
2806 {
2807 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
2808
2809 return pVPUHalContext->u32FWShareInfoAddr[u8Offset];
2810 }
2811
2812 #if defined(VDEC_FW31)
HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)2813 MS_VIRT HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)
2814 {
2815 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
2816 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
2817 MS_VIRT VsyncBridgeOffset = 0;
2818
2819 if (VPUSHMAddr != 0) // TEE project
2820 {
2821 if ((u8Offset == 0) || (u8Offset == 1))
2822 {
2823 VsyncBridgeOffset = VSYNC_BRIDGE_OFFSET;
2824 }
2825 else
2826 {
2827 VsyncBridgeOffset = VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
2828 }
2829 }
2830 else // normal project
2831 {
2832 if ((u8Offset == 0) || (u8Offset == 1))
2833 {
2834 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_OFFSET;
2835 }
2836 else
2837 {
2838 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
2839 }
2840 }
2841
2842 return VsyncBridgeOffset;
2843 }
2844
HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)2845 MS_VIRT HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)
2846 {
2847 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
2848 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
2849 MS_VIRT VsyncBridgeExtOffset = 0;
2850
2851 if (VPUSHMAddr != 0) // TEE project
2852 {
2853 if ((u8Offset == 0) || (u8Offset == 1))
2854 {
2855 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_OFFSET;
2856 }
2857 else
2858 {
2859 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
2860 }
2861 }
2862 else // normal project
2863 {
2864 if ((u8Offset == 0) || (u8Offset == 1))
2865 {
2866 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_OFFSET;
2867 }
2868 else
2869 {
2870 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
2871 }
2872 }
2873
2874 return VsyncBridgeExtOffset;
2875 }
2876 #endif
2877
HAL_VPU_EX_IsPowered(void)2878 MS_BOOL HAL_VPU_EX_IsPowered(void)
2879 {
2880 return pVPUHalContext->_bVPUPowered;
2881 }
2882
HAL_VPU_EX_IsRsted(void)2883 MS_BOOL HAL_VPU_EX_IsRsted(void)
2884 {
2885 return pVPUHalContext->_bVPURsted;
2886 }
2887
HAL_VPU_EX_IsEVDR2(void)2888 MS_BOOL HAL_VPU_EX_IsEVDR2(void)
2889 {
2890 #ifdef EVDR2
2891 return TRUE;
2892 #else
2893 return FALSE;
2894 #endif
2895 }
2896
HAL_VPU_EX_MVDInUsed(void)2897 MS_BOOL HAL_VPU_EX_MVDInUsed(void)
2898 {
2899 //MVD is in used for MVD or HVD_TSP mode.
2900 MS_U8 i;
2901 MS_U8 u8UseCnt = 0;
2902
2903 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
2904 {
2905 if ((pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_MVD) ||
2906 #ifdef VDEC3
2907 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_EVD) ||
2908 #endif
2909 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_HVD) )
2910 {
2911 u8UseCnt++;
2912 }
2913 }
2914
2915 VPU_MSG_DBG("MVD u8UseCnt=%d\n", u8UseCnt);
2916
2917 if (u8UseCnt != 0)
2918 {
2919 return TRUE;
2920 }
2921 else
2922 {
2923 return FALSE;
2924 }
2925 }
2926
HAL_VPU_EX_HVDInUsed(void)2927 MS_BOOL HAL_VPU_EX_HVDInUsed(void)
2928 {
2929 //HVD is in used for HVD or MVD in sub stream.
2930 MS_U8 i;
2931 MS_U8 u8UseCnt = 0;
2932 MS_BOOL bMVDTriggerHVD = FALSE;
2933 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
2934 {
2935 #ifdef VDEC3
2936 bMVDTriggerHVD = (E_VPU_EX_DECODER_MVD == pVPUHalContext->_stVPUStream[i].eDecodertype) &&
2937 (pVPUHalContext->u8HALId[i] == 1) &&
2938 (E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod);
2939 #else
2940 bMVDTriggerHVD = (E_VPU_EX_DECODER_MVD == pVPUHalContext->_stVPUStream[i].eDecodertype) &&
2941 (E_HAL_VPU_SUB_STREAM0 == pVPUHalContext->_stVPUStream[i].eStreamId) &&
2942 (E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod);
2943 #endif
2944
2945 if(bMVDTriggerHVD)
2946 {
2947 VPU_MSG_DBG("%s i:%d eDecodertype:%d u8DecMod:%d\n",__FUNCTION__,i,pVPUHalContext->_stVPUStream[i].eDecodertype,pVPUHalContext->_stVPUDecMode.u8DecMod);
2948 }
2949
2950 if ((E_VPU_EX_DECODER_HVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
2951 #ifdef VDEC3
2952 ||(E_VPU_EX_DECODER_EVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
2953 #endif
2954 ||(TRUE == bMVDTriggerHVD)
2955 )
2956 {
2957 u8UseCnt++;
2958 }
2959 }
2960
2961 VPU_MSG_DBG("HVD u8UseCnt=%d\n", u8UseCnt);
2962
2963 if (u8UseCnt != 0)
2964 {
2965 return TRUE;
2966 }
2967 else
2968 {
2969 return FALSE;
2970 }
2971 }
2972
HAL_VPU_EX_Mutex_Lock(void)2973 void HAL_VPU_EX_Mutex_Lock(void)
2974 {
2975 _HAL_VPU_Entry();
2976 }
2977
HAL_VPU_EX_Mutex_UnLock(void)2978 void HAL_VPU_EX_Mutex_UnLock(void)
2979 {
2980 _HAL_VPU_Release();
2981 }
2982
2983 #ifdef VDEC3
HAL_VPU_EX_EVDInUsed(void)2984 MS_BOOL HAL_VPU_EX_EVDInUsed(void)
2985 {
2986 MS_U8 i;
2987 MS_U8 u8UseCnt = 0;
2988
2989 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
2990 {
2991 if (E_VPU_EX_DECODER_EVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
2992 {
2993 u8UseCnt++;
2994 }
2995 }
2996
2997 VPU_MSG_DBG("EVD u8UseCnt=%d\n", u8UseCnt);
2998
2999 if (u8UseCnt != 0)
3000 {
3001 return TRUE;
3002 }
3003 else
3004 {
3005 return FALSE;
3006 }
3007 }
3008
3009 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VPU_EX_G2VP9InUsed(void)3010 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void)
3011 {
3012 MS_U8 i;
3013 MS_U8 u8UseCnt = 0;
3014
3015 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3016 {
3017 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[i].eDecodertype)
3018 {
3019 u8UseCnt++;
3020 }
3021 }
3022
3023 VPU_MSG_DBG("G2 VP9 u8UseCnt=%d\n", u8UseCnt);
3024
3025 if (u8UseCnt != 0)
3026 {
3027 return TRUE;
3028 }
3029 else
3030 {
3031 return FALSE;
3032 }
3033 }
3034 #endif
3035 #endif
3036
3037 //-----------------------------------------------------------------------------
3038 /// @brief \b Function \b Name: MDrv_HVD_EX_SetDbgLevel()
3039 /// @brief \b Function \b Description: Set debug level
3040 /// @param -elevel \b IN : debug level
3041 //-----------------------------------------------------------------------------
HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)3042 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)
3043 {
3044 printf("%s eLevel=0x%x\n", __FUNCTION__, eLevel);
3045
3046 switch (eLevel)
3047 {
3048 case E_VPU_EX_UART_LEVEL_ERR:
3049 {
3050 u32VpuUartCtrl = E_VPU_UART_CTRL_ERR;
3051 break;
3052 }
3053 case E_VPU_EX_UART_LEVEL_INFO:
3054 {
3055 u32VpuUartCtrl = E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_ERR;
3056 break;
3057 }
3058 case E_VPU_EX_UART_LEVEL_DBG:
3059 {
3060 u32VpuUartCtrl = E_VPU_UART_CTRL_DBG | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO;
3061 break;
3062 }
3063 case E_VPU_EX_UART_LEVEL_TRACE:
3064 {
3065 u32VpuUartCtrl = E_VPU_UART_CTRL_TRACE | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_DBG;
3066 break;
3067 }
3068 case E_VPU_EX_UART_LEVEL_FW:
3069 {
3070 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3071 break;
3072 }
3073 default:
3074 {
3075 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3076 break;
3077 }
3078 }
3079 }
3080
HAL_VPU_EX_GetFWVer(MS_U32 u32Id,VPU_EX_FWVerType eVerType)3081 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType)
3082 {
3083 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
3084 MS_U32 u32CmdArg = (MS_U32)eVerType;
3085 MS_U32 u32Version = 0xFFFFFFFF;
3086 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_VERSION, u32CmdArg);
3087 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
3088 {
3089 VPU_MSG_ERR("E_DUAL_VERSION NG eCtrlRet=%x\n", eCtrlRet);
3090 return u32Version;
3091 }
3092
3093 MS_BOOL bRet = false;
3094 MS_U32 u32TimeOut = 0xFFFFFFFF;
3095
3096 while(--u32TimeOut)
3097 {
3098 if(HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0))
3099 {
3100 bRet = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, &u32Version);
3101 if (false == bRet)
3102 {
3103 VPU_MSG_ERR("E_DUAL_VERSION NG bRet=%x\n", bRet);
3104 return u32Version;
3105 }
3106
3107 _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR);
3108 VPU_MSG_DBG("E_DUAL_VERSION arg=%x u32Version = 0x%x\n", u32CmdArg, u32Version);
3109 return u32Version;
3110 }
3111 }
3112
3113 VPU_MSG_ERR("get E_DUAL_VERSION=%x timeout", eVerType);
3114
3115 return u32Version;
3116 }
3117
HAL_VPU_EX_NotSupportDS(void)3118 MS_BOOL HAL_VPU_EX_NotSupportDS(void)
3119 {
3120 return FALSE;
3121 }
3122
3123 //-----------------------------------------------------------------------------
3124 /// @brief \b Function \b Name: HAL_VPU_EX_MIU1BASE()
3125 /// @brief \b Function \b Description: Get VPU MIU base address
3126 /// @return - vpu MIU1 base
3127 //-----------------------------------------------------------------------------
HAL_VPU_EX_MIU1BASE(void)3128 MS_VIRT HAL_VPU_EX_MIU1BASE(void)
3129 {
3130 return VPU_MIU1BASE_ADDR;
3131 }
3132
3133
HAL_VPU_EX_GetSHMAddr(void)3134 MS_VIRT HAL_VPU_EX_GetSHMAddr(void)
3135 {
3136 if(pVPUHalContext->bEnableVPUSecureMode == FALSE)
3137 {
3138 return 0;
3139 }
3140 return pVPUHalContext->u32VPUSHMAddr;
3141 }
HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)3142 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)
3143 {
3144 pVPUHalContext->bEnableVPUSecureMode = enable;
3145 return TRUE;
3146 }
3147
HAL_VPU_EX_CHIP_Capability(void * pHWCap)3148 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap)
3149 {
3150 ((VDEC_HwCap*)pHWCap)->u8Cap_Support_Decoder_Num = 2;
3151
3152 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG2 = TRUE;
3153 ((VDEC_HwCap*)pHWCap)->bCap_Support_H263 = TRUE;
3154 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG4 = TRUE;
3155 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX311 = TRUE;
3156 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX412 = TRUE;
3157 ((VDEC_HwCap*)pHWCap)->bCap_Support_FLV = TRUE;
3158 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1ADV = TRUE;
3159 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1MAIN = TRUE;
3160
3161 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV8 = TRUE;
3162 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV9 = TRUE;
3163 ((VDEC_HwCap*)pHWCap)->bCap_Support_H264 = TRUE;
3164 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS = TRUE;
3165 ((VDEC_HwCap*)pHWCap)->bCap_Support_MJPEG = TRUE;
3166 ((VDEC_HwCap*)pHWCap)->bCap_Support_MVC = TRUE;
3167 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP8 = TRUE;
3168 ((VDEC_HwCap*)pHWCap)->bCap_Support_HEVC = TRUE;
3169 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP9 = FALSE;
3170 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS_PLUS = TRUE;
3171
3172 return TRUE;
3173 }
3174
3175 //-----------------------------------------------------------------------------
3176 /// @brief \b Function \b Name: HAL_VPU_EX_GetCodecCapInfo()
3177 /// @brief \b Function \b Description: Get chip codec capability (for vudu)
3178 /// @return - success/fail
3179 //-----------------------------------------------------------------------------
HAL_VPU_EX_GetCodecCapInfo(int eCodecType,VDEC_EX_CODEC_CAP_INFO * pCodecCapInfo)3180 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo)
3181 {
3182 #define MAX_CAPABILITY_INFO_NUM 8
3183 #define MAX_CODEC_TYPE_NUM 18
3184
3185 unsigned int capability[MAX_CODEC_TYPE_NUM][MAX_CAPABILITY_INFO_NUM] =
3186 {
3187 //width, height , frmrate, profile, level, version bit rate reserved2
3188 { 0, 0, 0, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_NONE
3189 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 80, 0},//E_HVD_EX_CODEC_TYPE_MPEG2
3190 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_H263_1, 40, 0},//E_HVD_EX_CODEC_TYPE_H263
3191 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP4_ASP, E_VDEC_EX_CODEC_LEVEL_MP4_L5, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MPEG4
3192 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_311, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX311
3193 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_6, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX412
3194 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_FLV_1, 80, 0},//E_HVD_EX_CODEC_TYPE_FLV
3195 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_VC1_AP, E_VDEC_EX_CODEC_LEVEL_VC1_L3, E_VDEC_EX_CODEC_VERSION_NONE, 45, 0},//E_HVD_EX_CODEC_TYPE_VC1_ADV
3196 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 45, 0},//E_HVD_EX_CODEC_TYPE_VC1_MAIN (RCV)
3197 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 20, 0},//E_HVD_EX_CODEC_TYPE_RV8
3198 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 20, 0},//E_HVD_EX_CODEC_TYPE_RV9
3199 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_4_2, E_VDEC_EX_CODEC_VERSION_NONE, 62, 0},//E_HVD_EX_CODEC_TYPE_H264
3200 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, E_VDEC_EX_CODEC_LEVEL_AVS_6010860, E_VDEC_EX_CODEC_VERSION_NONE, 60, 0},//E_HVD_EX_CODEC_TYPE_AVS
3201 { 640, 480, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 10, 0},//E_HVD_EX_CODEC_TYPE_MJPEG
3202 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_4_2, E_VDEC_EX_CODEC_VERSION_NONE, 62, 0},//E_HVD_EX_CODEC_TYPE_MVC
3203 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 50, 0},//E_HVD_EX_CODEC_TYPE_VP8
3204 { 2048, 1088, 60, E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, E_VDEC_EX_CODEC_LEVEL_H265_4_1_HT, E_VDEC_EX_CODEC_VERSION_NONE, 50, 0},//E_HVD_EX_CODEC_TYPE_HEVC
3205 { 2048, 1088, 60, E_VDEC_EX_CODEC_PROFILE_VP9_2, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 30, 0},//E_HVD_EX_CODEC_TYPE_VP9
3206 };
3207
3208 if(eCodecType < MAX_CODEC_TYPE_NUM)
3209 {
3210 pCodecCapInfo->u16CodecCapWidth = capability[eCodecType][0];
3211 pCodecCapInfo->u16CodecCapHeight = capability[eCodecType][1];
3212 pCodecCapInfo->u8CodecCapFrameRate = capability[eCodecType][2];
3213 pCodecCapInfo->u8CodecCapProfile = capability[eCodecType][3];
3214 pCodecCapInfo->u8CodecCapLevel = capability[eCodecType][4];
3215 pCodecCapInfo->u8CodecCapVersion = capability[eCodecType][5];
3216 pCodecCapInfo->u32BitRate = capability[eCodecType][6];
3217 return TRUE;
3218 }
3219 else
3220 {
3221 return FALSE;
3222 }
3223 }
3224
3225 #ifdef VDEC3
HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType,MS_U8 u8TypeBit)3226 void HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit)
3227 {
3228 (void) u32Id;
3229 BBU_STATE *bbu_state;
3230
3231 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3232 || (eDecType == E_VPU_EX_DECODER_VP8)
3233 #if SUPPORT_G2VP9
3234 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3235 #endif
3236 )
3237 {
3238 // MVD should not call this function.
3239 // VP8 and G2_VP9 don't have the concept of BBU, so we just return.
3240 return;
3241 }
3242
3243 switch (eDecType)
3244 {
3245 case E_VPU_EX_DECODER_EVD:
3246 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3247 break;
3248 case E_VPU_EX_DECODER_HVD:
3249 case E_VPU_EX_DECODER_RVD:
3250 case E_VPU_EX_DECODER_MVC:
3251 default:
3252 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3253 break;
3254 }
3255
3256 bbu_state[u32BBUId].u8RegSetting |= u8TypeBit;
3257 return;
3258 }
3259
HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType,MS_U8 u8TypeBit)3260 MS_BOOL HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit)
3261 {
3262 (void) u32Id;
3263 BBU_STATE *bbu_state;
3264
3265 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3266 || (eDecType == E_VPU_EX_DECODER_VP8)
3267 #if SUPPORT_G2VP9
3268 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3269 #endif
3270 )
3271 {
3272 // MVD should not call this function.
3273 // VP8 and G2_VP9 don't have the concept of BBU, so we just return TRUE and not set related registers.
3274 return TRUE;
3275 }
3276
3277 switch (eDecType)
3278 {
3279 case E_VPU_EX_DECODER_EVD:
3280 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3281 break;
3282 case E_VPU_EX_DECODER_HVD:
3283 case E_VPU_EX_DECODER_RVD:
3284 case E_VPU_EX_DECODER_MVC:
3285 default:
3286 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3287 break;
3288 }
3289
3290 return (bbu_state[u32BBUId].u8RegSetting & u8TypeBit);
3291 }
3292
HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType)3293 void HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType)
3294 {
3295 (void) u32Id;
3296 BBU_STATE *bbu_state;
3297
3298 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3299 || (eDecType == E_VPU_EX_DECODER_VP8)
3300 #if SUPPORT_G2VP9
3301 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3302 #endif
3303 )
3304 {
3305 // MVD should not call this function.
3306 // VP8 and G2_VP9 don't have the concept of BBU, so we just return.
3307 return;
3308 }
3309
3310 switch (eDecType)
3311 {
3312 case E_VPU_EX_DECODER_EVD:
3313 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3314 break;
3315 case E_VPU_EX_DECODER_HVD:
3316 case E_VPU_EX_DECODER_RVD:
3317 case E_VPU_EX_DECODER_MVC:
3318 default:
3319 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3320 break;
3321 }
3322
3323 if (bbu_state[u32BBUId].u32Used == 0)
3324 {
3325 bbu_state[u32BBUId].u8RegSetting = 0;
3326 }
3327
3328 return;
3329 }
3330
HAL_VPU_EX_GetBBUId(MS_U32 u32Id,VPU_EX_TaskInfo * pTaskInfo,MS_BOOL bShareBBU)3331 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bShareBBU)
3332 {
3333 MS_U32 i, max_bbu_cnt;
3334 MS_U32 retBBUId = HAL_VPU_INVALID_BBU_ID;
3335
3336 if(pTaskInfo == NULL)
3337 return retBBUId;
3338
3339 BBU_STATE *bbu_state;
3340 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
3341 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3342
3343 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3344
3345 pVPUHalContext->u8HALId[u8TaskId] = pTaskInfo->u8HalId;
3346
3347 /* HVD_EX_MSG_ERR("[%d] DecType=0x%x \n", u32Id & 0xFF, pTaskInfo->eDecType);
3348 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3349 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3350
3351 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3352 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3353
3354 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3355 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3356 */
3357 #if 1
3358 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3359 {
3360 max_bbu_cnt = MAX_MVD_SLQ_COUNT;
3361 if (bTSP)
3362 {
3363 if ((u8TaskId < MAX_MVD_SLQ_COUNT) && (slq_state[u8TaskId].u32Used == 0))
3364 {
3365 VPRINTF("[NDec][0x%x][%d] MVD bTSP, use bbu %d \n", u32Id, u8TaskId, u8TaskId);
3366 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3367 slq_state[u8TaskId].bTSP = TRUE;
3368 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3369 return u8TaskId;
3370 }
3371 }
3372 else
3373 {
3374 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3375 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3376 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3377 {
3378 if (slq_state[i].u32Used != 0)
3379 {
3380 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && slq_state[i].bTSP == FALSE)
3381 {
3382 shared_bbu_idx = i; // recored the first used MM bbu for sharing
3383 }
3384 }
3385 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3386 {
3387 avaliable_bbu_idx = i; // recored the first empty bbu
3388 }
3389 }
3390
3391 /* VPRINTF("[NDec][0x%x][%d] MVD bShareBBU %d, shared_bbu %d, avail_bbu %d \n", u32Id, u8TaskId, bShareBBU, shared_bbu_idx, avaliable_bbu_idx); */
3392
3393 if ((bShareBBU == TRUE) && (shared_bbu_idx != HAL_VPU_INVALID_BBU_ID)) { // In Nstream mode, first priority is sharing bbu
3394 slq_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3395 slq_state[shared_bbu_idx].bTSP = FALSE;
3396 slq_state[shared_bbu_idx].bUsedbyMVD = TRUE;
3397 VPRINTF("[NDec][0x%x][%d] MVD shared_bbu %d \n", u32Id, u8TaskId, shared_bbu_idx);
3398 return shared_bbu_idx;
3399 }
3400 else if (slq_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3401 slq_state[u8TaskId].u32Used |= (1 << u8TaskId);
3402 slq_state[u8TaskId].bTSP = FALSE;
3403 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3404
3405 if (bShareBBU == FALSE)
3406 {
3407 slq_state[u8TaskId].bTSP = TRUE;
3408 VPRINTF("[NDec] MVD occupy one BBU_ID \n");
3409 }
3410 VPRINTF("[NDec][0x%x][%d] MVD u8TaskId %d \n", u32Id, u8TaskId, u8TaskId);
3411 return u8TaskId;
3412 }
3413 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID && avaliable_bbu_idx < max_bbu_cnt) { // 3rd priority is avaliable bbu id
3414 slq_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3415 slq_state[avaliable_bbu_idx].bTSP = FALSE;
3416 slq_state[avaliable_bbu_idx].bUsedbyMVD = TRUE;
3417
3418 if (bShareBBU == FALSE)
3419 {
3420 slq_state[avaliable_bbu_idx].bTSP = TRUE;
3421 VPRINTF("[NDec] MVD occupy one BBU_ID \n");
3422 }
3423 VPRINTF("[NDec][0x%x][%d] MVD avaliable_bbu_idx %d \n", u32Id, u8TaskId, avaliable_bbu_idx);
3424 return avaliable_bbu_idx;
3425 }
3426 else {
3427 VPU_MSG_ERR("ERROR!!! MVD can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3428 }
3429 }
3430 }
3431 #if SUPPORT_G2VP9
3432 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3433 {
3434 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3435 // Don't care the return value, G2_VP9 will not use it.
3436 return 0;
3437 }
3438 #endif
3439 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3440 {
3441 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3442 // Don't care the return value, VP8 will not use it.
3443 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3444 return u8Offset;
3445 //return 0;
3446 }
3447 else
3448 {
3449 switch (pTaskInfo->eDecType)
3450 {
3451 case E_VPU_EX_DECODER_EVD:
3452 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3453 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3454 break;
3455 case E_VPU_EX_DECODER_HVD:
3456 case E_VPU_EX_DECODER_RVD:
3457 case E_VPU_EX_DECODER_MVC:
3458 default:
3459 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3460 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3461 break;
3462 }
3463
3464 // FIXME: TSP assume bbu id = u8TaskId, so it does not support N decode. Use the same logic with MM to support it
3465 if (bTSP)
3466 {
3467 if ((u8TaskId < max_bbu_cnt) && (bbu_state[u8TaskId].u32Used == 0) && (slq_state[u8TaskId].u32Used == 0))
3468 {
3469 VPRINTF("[NDec][0x%x][%d] bTSP, use bbu %d \n", u32Id, u8TaskId, u8TaskId);
3470 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3471 bbu_state[u8TaskId].bTSP = TRUE;
3472 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3473 slq_state[u8TaskId].bTSP = TRUE;
3474 slq_state[u8TaskId].bUsedbyMVD = FALSE;
3475 return u8TaskId;
3476 }
3477 }
3478 else
3479 {
3480 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3481 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3482 for (i = 0; i < max_bbu_cnt; i++)
3483 {
3484 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && bbu_state[i].u32Used != 0)
3485 {
3486 if (bbu_state[i].bTSP == FALSE)
3487 {
3488 shared_bbu_idx = i;
3489 }
3490 }
3491 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3492 {
3493 avaliable_bbu_idx = i;
3494 }
3495 }
3496
3497 VPRINTF("[NDec][0x%x][%d] bShareBBU %d, shared_bbu %d, avail_bbu %d \n", u32Id, u8TaskId, bShareBBU, shared_bbu_idx, avaliable_bbu_idx);
3498
3499 if ((bShareBBU == TRUE) && (shared_bbu_idx != HAL_VPU_INVALID_BBU_ID)) { // // In Nstream mode, first priority is sharing bbu
3500 bbu_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3501 VPRINTF("[NDec][0x%x][%d] shared_bbu %d \n", u32Id, u8TaskId, shared_bbu_idx);
3502 return shared_bbu_idx;
3503 }
3504 else if (bbu_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3505 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3506
3507 if (bShareBBU == FALSE)
3508 {
3509 bbu_state[u8TaskId].bTSP = TRUE;
3510 VPRINTF("[NDec] occupy one BBU_ID \n");
3511 }
3512 VPRINTF("[NDec][0x%x][%d] u8TaskId %d \n", u32Id, u8TaskId, u8TaskId);
3513 return u8TaskId;
3514 }
3515 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID && avaliable_bbu_idx < max_bbu_cnt) { // 3rd priority is avaliable bbu id
3516 bbu_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3517
3518 if (bShareBBU == FALSE)
3519 {
3520 bbu_state[avaliable_bbu_idx].bTSP = TRUE;
3521 VPRINTF("[NDec] occupy one BBU_ID \n");
3522 }
3523 VPRINTF("[NDec][0x%x][%d] avaliable_bbu_idx %d \n", u32Id, u8TaskId, avaliable_bbu_idx);
3524 return avaliable_bbu_idx;
3525 }
3526 else {
3527 VPU_MSG_ERR("ERROR!!! can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3528 }
3529 }
3530 }
3531 #else // The following source code is wiser selecting BBU id. Howerver, it need HW to support and we mark it temporarily.
3532 MS_U32 j;
3533 MS_BOOL Got = FALSE;
3534 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3535 {
3536 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3537 {
3538 if(slq_state[i].u32Used != 0)
3539 {
3540 if(!bTSP && slq_state[i].bTSP == FALSE) // MVD non-first MM case
3541 {
3542 retBBUId = i;
3543 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3544 slq_state[retBBUId].bTSP = bTSP;
3545 slq_state[retBBUId].bUsedbyMVD = TRUE;
3546 return retBBUId;
3547 }
3548 }
3549 else if(!Got && slq_state[i].u32Used == 0) // MVD first MM or TS case
3550 {
3551 if(i < MAX_EVD_BBU_COUNT) // Trend to select used EVD BBU id
3552 {
3553 if(pVPUHalContext->stEVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stEVD_BBU_STATE[i].bTSP == FALSE)
3554 {
3555 Got = TRUE;
3556 retBBUId = i;
3557 }
3558 }
3559
3560 if(!Got && i < MAX_HVD_BBU_COUNT) // Trend to select used HVD BBU id
3561 {
3562 if(pVPUHalContext->stHVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stHVD_BBU_STATE[i].bTSP == FALSE)
3563 {
3564 Got = TRUE;
3565 retBBUId = i;
3566 }
3567 }
3568
3569 if(!Got && retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used EVD BBU id, select the first BBU_ID
3570 retBBUId = i;
3571 }
3572 }
3573 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
3574 {
3575 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3576 slq_state[retBBUId].bTSP = bTSP;
3577 slq_state[retBBUId].bUsedbyMVD = TRUE;
3578 }
3579 }
3580 #if SUPPORT_G2VP9
3581 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3582 {
3583 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3584 // Don't care the return value, G2_VP9 will not use it.
3585 return 0;
3586 }
3587 #endif
3588 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3589 {
3590 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3591 // Don't care the return value, VP8 will not use it.
3592 return 0;
3593 }
3594 else // HVD/EVD case
3595 {
3596 switch (pTaskInfo->eDecType)
3597 {
3598 case E_VPU_EX_DECODER_EVD:
3599 case E_VPU_EX_DECODER_G2VP9:
3600 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3601 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3602 break;
3603 case E_VPU_EX_DECODER_HVD:
3604 case E_VPU_EX_DECODER_RVD:
3605 case E_VPU_EX_DECODER_MVC:
3606 default:
3607 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3608 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3609 break;
3610 }
3611
3612 for (i = 0; i < max_bbu_cnt; i++)
3613 {
3614 if(bbu_state[i].u32Used != 0)
3615 {
3616 if(!bTSP && bbu_state[i].bTSP == FALSE) // HVD/EVD non-first MM case
3617 {
3618 retBBUId = i;
3619 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3620 bbu_state[retBBUId].bTSP = bTSP;
3621 return retBBUId;
3622 }
3623 }
3624 else if(bbu_state[i].u32Used == 0) // HVD/EVD first MM or TS case
3625 {
3626 if(i < MAX_MVD_SLQ_COUNT)
3627 {
3628 if(!bTSP) //HVD/EVD first MM case
3629 {
3630 if( slq_state[i].u32Used != 0 && slq_state[i].bUsedbyMVD== TRUE) // HVD/EVD MM will trend to select used MVD SLQ id
3631 {
3632 retBBUId = i;
3633 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3634 bbu_state[retBBUId].bTSP = bTSP;
3635 return retBBUId;
3636 }
3637
3638 if(retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used MVD SLQ id, select the first BBU_ID
3639 retBBUId = i;
3640 }
3641 else if(slq_state[i].u32Used == 0) //HVD/EVD TSP case, just find a empty slq id
3642 {
3643 retBBUId = i;
3644 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3645 bbu_state[retBBUId].bTSP = bTSP;
3646 slq_state[retBBUId].bUsedbyMVD = FALSE;
3647 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3648 slq_state[retBBUId].bTSP = bTSP;
3649 return retBBUId;
3650 }
3651 }
3652 }
3653 }
3654 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
3655 {
3656 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3657 bbu_state[retBBUId].bTSP = bTSP;
3658 if(bTSP)
3659 {
3660 slq_state[retBBUId].bUsedbyMVD = FALSE;
3661 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3662 slq_state[retBBUId].bTSP = bTSP;
3663 }
3664 }
3665 }
3666 #endif
3667 return retBBUId;
3668 }
3669
HAL_VPU_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_TaskInfo * pTaskInfo)3670 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo)
3671 {
3672 MS_U32 max_bbu_cnt;
3673 BBU_STATE *bbu_state;
3674 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
3675
3676 if(pTaskInfo == NULL)
3677 return FALSE;
3678 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3679 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3680
3681 HVD_EX_MSG_DBG("[%d] DecType=0x%x \n", (int)(u32Id & 0xFF), pTaskInfo->eDecType);
3682 /* MS_U32 i;
3683 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3684 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3685
3686 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3687 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3688
3689 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3690 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3691 */
3692 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3693 {
3694 // TO DO
3695 if(u32BBUId < MAX_MVD_SLQ_COUNT)
3696 {
3697 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
3698 slq_state[u32BBUId].bTSP = FALSE;
3699 slq_state[u32BBUId].bUsedbyMVD = FALSE;
3700 return TRUE;
3701 }
3702 }
3703 #if SUPPORT_G2VP9
3704 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3705 {
3706 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3707 return TRUE;
3708 }
3709 #endif
3710 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3711 {
3712 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3713 return TRUE;
3714 }
3715 else
3716 {
3717 switch (pTaskInfo->eDecType)
3718 {
3719 case E_VPU_EX_DECODER_EVD:
3720 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3721 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3722 break;
3723 case E_VPU_EX_DECODER_HVD:
3724 case E_VPU_EX_DECODER_RVD:
3725 case E_VPU_EX_DECODER_MVC:
3726 default:
3727 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3728 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3729 break;
3730 }
3731
3732 if (u32BBUId < max_bbu_cnt)
3733 {
3734 bbu_state[u32BBUId].u32Used &= ~(1 << u8TaskId);
3735 bbu_state[u32BBUId].bTSP = FALSE;
3736
3737 if (bTSP)
3738 {
3739 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
3740 slq_state[u32BBUId].bTSP = FALSE;
3741 slq_state[u32BBUId].bUsedbyMVD = FALSE;
3742 }
3743
3744 #if 1
3745 HAL_VPU_EX_ClearBBUSetting(u32Id, u32BBUId, pTaskInfo->eDecType);
3746 #else
3747 if (bbu_state[u32BBUId].u32Used == 0)
3748 {
3749 bbu_state[u32BBUId].u8RegSetting = 0; // clear record of both NAL_TBL and ES_BUFFER
3750 }
3751 #endif
3752
3753 return TRUE;
3754 }
3755 }
3756 return FALSE;
3757 }
3758
HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)3759 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)
3760 {
3761 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3762
3763 if (CHECK_NULL_PTR(pstVBBU))
3764 return 0;
3765 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
3766 MS_U32 u32RdPtr = pstVBBU->u32RdPtr;
3767 MS_U32 u32Vacancy = 0;
3768
3769 if (u32WrPtr == u32RdPtr)
3770 {
3771 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT;
3772 }
3773 else if (u32WrPtr > u32RdPtr)
3774 {
3775 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT - (u32WrPtr - u32RdPtr);
3776 }
3777 else
3778 {
3779 u32Vacancy = u32RdPtr - u32WrPtr - 1;
3780 }
3781
3782 return u32Vacancy;
3783 }
3784
HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)3785 MS_U32 HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)
3786 {
3787 return MAX_VDEC_VBBU_ENTRY_COUNT;
3788 }
3789
HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)3790 MS_PHY HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)
3791 {
3792 return pVPUHalContext->u32FWCodeAddr;
3793 }
3794
HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)3795 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
3796 {
3797 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3798 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3799
3800 if (CHECK_NULL_PTR(pstVBBU))
3801 return FALSE;
3802 MsOS_ReadMemory();
3803 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry *) &pstVBBU->stEntry[pstVBBU->u32RdPtr];
3804
3805 if(NULL == stEntry)
3806 {
3807 return 0;
3808 }
3809
3810 // ALOGE("JJJ1: %d %d %d", pstVBBU->u32RdPtr, pstVBBU->u32WrPtr, stEntry->u32Offset);
3811 if (pstVBBU->u32RdPtr == pstVBBU->u32WrPtr)
3812 {
3813 return HAL_VPU_EX_GetESWritePtr(u32Id, u32VBBUAddr);
3814 }
3815 else
3816 {
3817 #if SUPPORT_G2VP9
3818 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
3819 {
3820 if (stEntry->u32Offset == 0)
3821 return 0;
3822 else
3823 return stEntry->u32Offset - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
3824 }
3825 else if(E_VPU_EX_DECODER_MVD == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
3826 {
3827 if(stEntry->u32Offset < 0x80000)
3828 {
3829 return pstVBBU->stEntry[((pstVBBU->u32RdPtr+MAX_VDEC_VBBU_ENTRY_COUNT)%(MAX_VDEC_VBBU_ENTRY_COUNT+1))].u32Offset;
3830 }
3831 else
3832 {
3833 return stEntry->u32Offset;
3834 }
3835 }
3836 else
3837 #else
3838 if(E_VPU_EX_DECODER_MVD == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
3839 {
3840 if(stEntry->u32Offset < 0xA000)
3841 {
3842 return pstVBBU->stEntry[((pstVBBU->u32RdPtr+MAX_VDEC_VBBU_ENTRY_COUNT)%(MAX_VDEC_VBBU_ENTRY_COUNT+1))].u32Offset;
3843 }
3844 else
3845 {
3846 return stEntry->u32Offset;
3847 }
3848 }
3849 else
3850 #endif
3851 {
3852 return stEntry->u32Offset;
3853 }
3854 }
3855 }
3856
HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)3857 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
3858 {
3859 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3860 VDEC_VBBU_Entry *stEntry;
3861
3862 MsOS_ReadMemory();
3863 if (CHECK_NULL_PTR(pstVBBU))
3864 return 0;
3865 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
3866
3867 if (u32WrPtr == 0)
3868 u32WrPtr = MAX_VDEC_VBBU_ENTRY_COUNT;
3869 else
3870 u32WrPtr--;
3871
3872 stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[u32WrPtr];
3873
3874 if(NULL == stEntry)
3875 {
3876 return 0;
3877 }
3878
3879 //ALOGE("JJJ2: %d %d %d %d", pstVBBU->u32RdPtr, u32WrPtr, stEntry->u32Offset, stEntry->u32Length);
3880 #if SUPPORT_G2VP9
3881 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3882 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
3883 {
3884 if (stEntry->u32Offset == 0)
3885 return 0;
3886 else
3887 return stEntry->u32Offset + stEntry->u32Length - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
3888 }
3889 else
3890 #endif
3891 {
3892 return stEntry->u32Offset + stEntry->u32Length;
3893 }
3894 }
3895
HAL_VPU_EX_Push2VBBU(MS_U32 u32Id,HAL_VPU_EX_PacketInfo * stVpuPkt,MS_VIRT u32VBBUAddr)3896 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr)
3897 {
3898 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3899
3900 if (CHECK_NULL_PTR(pstVBBU) || CHECK_NULL_PTR(stVpuPkt))
3901 return FALSE;
3902 MsOS_ReadMemory();
3903 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[pstVBBU->u32WrPtr];
3904 MS_U32 u32NewWrPtr;
3905
3906 u32NewWrPtr = pstVBBU->u32WrPtr + 1;
3907 if (u32NewWrPtr == (MAX_VDEC_VBBU_ENTRY_COUNT + 1))
3908 {
3909 u32NewWrPtr = 0;
3910 }
3911
3912 if (u32NewWrPtr == pstVBBU->u32RdPtr) return FALSE;
3913
3914 stEntry->u32Offset = stVpuPkt->u32Offset;
3915 #if SUPPORT_G2VP9
3916 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3917 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
3918 {
3919 stEntry->u32Offset += pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
3920 }
3921 #endif
3922 stEntry->u32Length = stVpuPkt->u32Length;
3923 stEntry->u64TimeStamp = stVpuPkt->u64TimeStamp;
3924 stEntry->u32ID_H = stVpuPkt->u32ID_H;
3925 stEntry->u32ID_L = stVpuPkt->u32ID_L;
3926
3927 MsOS_FlushMemory();
3928 pstVBBU->u32WrPtr = u32NewWrPtr;
3929
3930 //ALOGE("JJJ3: %d", pstVBBU->u32WrPtr);
3931
3932 MsOS_FlushMemory();
3933
3934 return TRUE;
3935 }
3936
HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)3937 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)
3938 {
3939 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3940
3941 if (CHECK_NULL_PTR(pstVBBU))
3942 return FALSE;
3943 return pstVBBU->u32RdPtr == pstVBBU->u32WrPtr;
3944 }
3945
3946 ///-----------------------------------------------------------------------------
3947 /// specify the command send to Mail box or DRAM
3948 /// @return TRUE or FALSE
3949 /// - TRUE, Mail box
3950 /// - FALSE, Dram
3951 /// @param u32Cmd \b IN: Command is going to be sned
3952 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)3953 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)
3954 {
3955 MS_BOOL bResult = TRUE;
3956
3957 switch (u32Cmd)
3958 {
3959 // *********** Runtime action Command
3960 /* case E_HVD_CMD_RELEASE_DISPQ:
3961 case E_HVD_CMD_UPDATE_DISPQ:
3962 case E_HVD_CMD_FLUSH_DEC_Q:
3963 case E_HVD_CMD_FLUSH:
3964 case E_HVD_CMD_PLAY:
3965 case E_HVD_CMD_PAUSE:
3966 case E_HVD_CMD_STOP:
3967 case E_HVD_CMD_STEP_DECODE:
3968 case E_HVD_CMD_SKIP_DEC:
3969 case E_HVD_CMD_DISP_I_DIRECT:*/
3970 // *********** Dual-Stream Create Task Command
3971 case E_DUAL_CMD_TASK0_HVD_BBU:
3972 case E_DUAL_CMD_TASK0_HVD_TSP:
3973 case E_DUAL_CMD_TASK0_MVD_SLQ:
3974 case E_DUAL_CMD_TASK0_MVD_TSP:
3975 case E_DUAL_CMD_TASK1_HVD_BBU:
3976 case E_DUAL_CMD_TASK1_HVD_TSP:
3977 case E_DUAL_CMD_MODE:
3978 #ifndef _WIN32
3979 case E_DUAL_CMD_TASK1_MVD_SLQ:
3980 case E_DUAL_CMD_TASK1_MVD_TSP:
3981 #endif
3982 case E_DUAL_CMD_DEL_TASK:
3983 case E_DUAL_CMD_SINGLE_TASK:
3984 case E_DUAL_VERSION:
3985 case E_DUAL_R2_CMD_EXIT:
3986 case E_DUAL_CMD_STC_MODE:
3987 #ifdef VDEC3
3988 case E_DUAL_R2_CMD_FBADDR:
3989 case E_DUAL_R2_CMD_FBSIZE:
3990 // *********** N-Streams
3991 case E_NST_CMD_TASK_HVD_TSP:
3992 case E_NST_CMD_TASK_HVD_BBU:
3993 case E_NST_CMD_TASK_MVD_TSP:
3994 case E_NST_CMD_TASK_MVD_SLQ:
3995 case E_NST_CMD_DEL_TASK:
3996 case E_NST_CMD_COMMON_MASK:
3997 case E_NST_CMD_COMMON_CMD1:
3998 #endif
3999 case E_DUAL_CMD_COMMON:
4000 {
4001 bResult = TRUE;
4002 }
4003 break;
4004 default:
4005 {
4006 bResult = FALSE;
4007 }
4008 break;
4009 }
4010
4011 return bResult;
4012 }
4013
4014 ///-----------------------------------------------------------------------------
4015 /// specify the command send to Mail box or DRAM
4016 /// @return TRUE or FALSE
4017 /// - TRUE, Mail box
4018 /// - FALSE, Dram
4019 /// @param u32Cmd \b IN: Command is going to be sned
4020 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)4021 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)
4022 {
4023 MS_BOOL bResult = TRUE;
4024
4025 switch (u32Cmd)
4026 {
4027 // *********** Runtime action Command
4028 case E_HVD_CMD_RELEASE_DISPQ:
4029 case E_HVD_CMD_UPDATE_DISPQ:
4030 case E_HVD_CMD_FLUSH_DEC_Q:
4031 case E_HVD_CMD_PAUSE:
4032 case E_HVD_CMD_FLUSH:
4033 case E_HVD_CMD_PLAY:
4034 case E_HVD_CMD_STOP:
4035 case E_HVD_CMD_SKIP_DEC:
4036 case E_HVD_CMD_DISP_I_DIRECT:
4037 case E_HVD_CMD_STEP_DECODE:
4038 case E_HVD_CMD_INC_DISPQ_NUM:
4039 case E_HVD_CMD_DYNAMIC_CONNECT_DISP_PATH:
4040 {
4041 bResult = TRUE;
4042 }
4043 break;
4044 default:
4045 {
4046 bResult = FALSE;
4047 }
4048 break;
4049 }
4050
4051 return bResult;
4052 }
4053
4054 ///-----------------------------------------------------------------------------
4055 /// Send message to HVD stream command queue
4056 /// @return TRUE or FALSE
4057 /// - TRUE, Success
4058 /// - FALSE, Failed
4059 /// @param u32DramAddr \b IN: address to be writen
4060 /// @param u32Msg \b IN: data to be writen
4061 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr,MS_U32 u32Msg)4062 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg)
4063 {
4064 MS_BOOL bResult = TRUE;
4065
4066 VPU_MSG_DBG("Send to Command Queue Address=0x%lx, msg=0x%x\n", (unsigned long)u32DramAddr, u32Msg);
4067
4068 WRITE_LONG(u32DramAddr,u32Msg);
4069
4070 return bResult;
4071 }
4072
4073 ///-----------------------------------------------------------------------------
4074 /// Read task share memory to specify that task command queue is empty or not
4075 /// @return TRUE or FALSE
4076 /// - TRUE, Empty
4077 /// - FALSE, Non empty
4078 /// @param u32Id \b IN: Task information
4079 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsEmpty(void * cmd_queue)4080 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue)
4081 {
4082 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4083 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4084 if (!cmd_q)
4085 {
4086 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4087 return FALSE;
4088 }
4089
4090 return cmd_q->u32HVD_STREAM_CMDQ_WD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4091 }
4092
4093 ///-----------------------------------------------------------------------------
4094 /// Read task share memory to specify that task command queue is full or not
4095 /// @return TRUE or FALSE
4096 /// - TRUE, Full
4097 /// - FALSE, Non full
4098 /// @param u32Id \b IN: Task information
4099 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsFull(void * cmd_queue)4100 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue)
4101 {
4102 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4103 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4104 if (!cmd_q)
4105 {
4106 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4107 return TRUE;
4108 }
4109 MS_U32 NewWD = cmd_q->u32HVD_STREAM_CMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4110
4111 if(NewWD >= HVD_CMDQ_DRAM_ST_SIZE)
4112 NewWD -= HVD_CMDQ_DRAM_ST_SIZE;
4113
4114 return NewWD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4115 }
4116
HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4117 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4118 {
4119 MS_U32 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4120 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4121 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4122
4123 #if HVD_ENABLE_MVC
4124 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4125 {
4126 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4127 }
4128 #endif
4129
4130 if (CHECK_NULL_PTR(cmd_q))
4131 {
4132 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4133 return bResult;
4134 }
4135 MS_VIRT u32CmdQWdPtr;
4136
4137 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR))
4138 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4139
4140 if (HAL_VPU_EX_DRAMCMDQueueIsFull(cmd_q))
4141 return E_HVD_COMMAND_QUEUE_FULL;
4142 else
4143 {
4144 u32CmdQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_CMDQ_WD);
4145 }
4146
4147 switch (u8CmdType)
4148 {
4149 case E_HVD_CMDQ_CMD:
4150 {
4151 u32Msg |= (u8TaskID << 24);
4152 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr, u32Msg);
4153
4154 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4155
4156 if (bResult)
4157 {
4158 if(cmd_q->u32HVD_STREAM_CMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE) >= HVD_CMDQ_DRAM_ST_SIZE )
4159 cmd_q->u32HVD_STREAM_CMDQ_WD = 0;
4160 else
4161 cmd_q->u32HVD_STREAM_CMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4162
4163 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4164 }
4165 break;
4166 }
4167 case E_HVD_CMDQ_ARG:
4168 {
4169 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4170 if (bResult)
4171 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4172 break;
4173 }
4174 default:
4175 {
4176 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4177 break;
4178 }
4179 }
4180
4181 MsOS_FlushMemory();
4182
4183 return bResult;
4184 }
4185
4186 ///-----------------------------------------------------------------------------
4187 /// Read task share memory to specify that task display command queue is empty or not
4188 /// @return TRUE or FALSE
4189 /// - TRUE, Empty
4190 /// - FALSE, Non empty
4191 /// @param u32Id \b IN: Task information
4192 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void * cmd_queue)4193 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue)
4194 {
4195 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4196 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4197 if (!cmd_q)
4198 {
4199 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4200 return FALSE;
4201 }
4202
4203 return cmd_q->u32HVD_STREAM_DISPCMDQ_WD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4204 }
4205
HAL_VPU_EX_DRAMDispCMDQueueIsFull(void * cmd_queue)4206 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue)
4207 {
4208 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4209 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4210 if (!cmd_q)
4211 {
4212 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4213 return TRUE;
4214 }
4215
4216 MS_U32 NewWD = cmd_q->u32HVD_STREAM_DISPCMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4217
4218 if(NewWD >= HVD_DISPCMDQ_DRAM_ST_SIZE)
4219 NewWD -= HVD_DISPCMDQ_DRAM_ST_SIZE;
4220
4221 return NewWD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4222 }
4223
HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4224 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4225 {
4226 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4227 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4228 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4229
4230 #if HVD_ENABLE_MVC
4231 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4232 {
4233 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4234 }
4235 #endif
4236
4237 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4238 //HVD_EX_MSG_DBG("DP shmAddr=%X u8TaskID = %X u8CmdType = %X u32Msg = %X\n", pShm, u8TaskID, u8CmdType, u32Msg);
4239
4240 if (CHECK_NULL_PTR(cmd_q))
4241 {
4242 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4243 return bResult;
4244 }
4245
4246 MS_VIRT u32DISPCMDQWdPtr;
4247
4248 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR))
4249 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4250
4251 if (HAL_VPU_EX_DRAMDispCMDQueueIsFull(cmd_q))
4252 return E_HVD_COMMAND_QUEUE_FULL;
4253 else
4254 {
4255 u32DISPCMDQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_DISPCMDQ_WD);
4256 }
4257
4258 // HVD_EX_MSG_DBG("VDispCmdQ_BASE_ADDR=%X PDispCmsQ_BASE_ADDR=%X u32DISPCMDQWdPtr=%X DISPCMDQ_TOTAL_SIZE = %X\n", cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, pVPUHalContext->u32FWCodeVAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, u32DISPCMDQWdPtr,HVD_DISPCMDQ_DRAM_ST_SIZE);
4259
4260 switch (u8CmdType)
4261 {
4262 case E_HVD_CMDQ_CMD:
4263 {
4264 u32Msg |= (u8TaskID << 24);
4265 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr, u32Msg);
4266
4267 MsOS_FlushMemory();
4268
4269 if (bResult)
4270 {
4271 cmd_q->u32HVD_STREAM_DISPCMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4272
4273 if (cmd_q->u32HVD_STREAM_DISPCMDQ_WD == HVD_DISPCMDQ_DRAM_ST_SIZE)
4274 cmd_q->u32HVD_STREAM_DISPCMDQ_WD = 0;
4275
4276 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4277 }
4278 break;
4279 }
4280 case E_HVD_CMDQ_ARG:
4281 {
4282 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4283 if (bResult)
4284 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4285 break;
4286 }
4287 default:
4288 {
4289 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4290 break;
4291 }
4292 }
4293
4294 MsOS_FlushMemory();
4295
4296 return bResult;
4297 }
4298
HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id,MS_VIRT u32BsAddr)4299 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr)
4300 {
4301 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4302 MS_U32 u32StAddr;
4303 MS_U8 u8TmpMiuSel;
4304
4305 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32BsAddr);
4306
4307 pVPUHalContext->u32BitstreamAddress[u8OffsetIdx] = u32StAddr; //20170110
4308
4309 return TRUE;
4310 }
4311 #endif
4312
HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)4313 void HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)
4314 {
4315 pVPUHalContext->bEnableDymanicFBMode = bEnable;
4316
4317 if(u32address >= HAL_MIU1_BASE)
4318 {
4319 pVPUHalContext->u32DynamicFBAddress = u32address-HAL_MIU1_BASE;
4320 }
4321 else
4322 {
4323 pVPUHalContext->u32DynamicFBAddress = u32address;
4324 }
4325
4326 pVPUHalContext->u32DynamicFBSize = u32Size;
4327 }
4328
_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4329 MS_SIZE _VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4330 {
4331 MS_SIZE FrameBufferSize = 0;
4332
4333 switch(eCodecType)
4334 {
4335 case E_VPU_EX_CODEC_TYPE_MPEG2:
4336 case E_VPU_EX_CODEC_TYPE_H263:
4337 case E_VPU_EX_CODEC_TYPE_MPEG4:
4338 case E_VPU_EX_CODEC_TYPE_DIVX311:
4339 case E_VPU_EX_CODEC_TYPE_DIVX412:
4340 case E_VPU_EX_CODEC_TYPE_FLV:
4341 FrameBufferSize = 0x1E00000;
4342 break;
4343 case E_VPU_EX_CODEC_TYPE_VC1_ADV:
4344 case E_VPU_EX_CODEC_TYPE_VC1_MAIN:
4345 FrameBufferSize = 0x6C00000;
4346 break;
4347 case E_VPU_EX_CODEC_TYPE_RV8:
4348 case E_VPU_EX_CODEC_TYPE_RV9:
4349 FrameBufferSize = 0x1B00000;
4350 break;
4351 case E_VPU_EX_CODEC_TYPE_VP8:
4352 FrameBufferSize = 0x1500000;
4353 break;
4354 case E_VPU_EX_CODEC_TYPE_H264:
4355 FrameBufferSize = 0x8200000;
4356 //FrameBufferSize = 0x7A00000; //UHD 122MB ,5 ref frame
4357 //FrameBufferSize = 0x7A80000; //UHD 4K2K 16:19 126.5MB
4358 //FrameBufferSize = 0x8E00000; //UHD 4K2K 16:19 142MB
4359 break;
4360 case E_VPU_EX_CODEC_TYPE_AVS:
4361 FrameBufferSize = 0x1B00000;
4362 break;
4363 case E_VPU_EX_CODEC_TYPE_MJPEG:
4364 FrameBufferSize = 0x2800000;
4365 break;
4366 case E_VPU_EX_CODEC_TYPE_MVC:
4367 FrameBufferSize = 0x4200000;
4368 break;
4369 case E_VPU_EX_CODEC_TYPE_HEVC:
4370 #if SUPPORT_MSVP9
4371 case E_VPU_EX_CODEC_TYPE_VP9:
4372 #endif
4373 FrameBufferSize = 0xA000000;
4374 break;
4375 #if !SUPPORT_MSVP9
4376 case E_VPU_EX_CODEC_TYPE_VP9:
4377 FrameBufferSize = 0x7800000;
4378 break;
4379 #endif
4380 default:
4381 FrameBufferSize = 0;
4382 break;
4383 }
4384
4385 return FrameBufferSize;
4386 }
4387
HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4388 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4389 {
4390 return _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
4391 }
4392
4393 #ifdef CMA_DRV_DIRECT_INIT
4394 // To-do: Taking the source type into consideration
HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType,VPU_EX_SrcMode eSrcMode,MS_U64 * offset,MS_SIZE * length,MS_U64 total_length,MS_SIZE unUseSize)4395 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode,
4396 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize)
4397 {
4398 MS_SIZE FrameBufferSize = 0;
4399
4400 if (!offset || !length)
4401 return FALSE;
4402
4403 total_length -= unUseSize;
4404 VPRINTF("[HAL][%s]:[%d] total_length:%llu, cType:%d, sType:%d\n", __FUNCTION__, __LINE__,
4405 (unsigned long long)total_length, (int)eCodecType, (int)eSrcMode);
4406
4407 FrameBufferSize = _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
4408
4409 if(FrameBufferSize == 0)
4410 {
4411 return FALSE;
4412 }
4413 VPRINTF("[HAL][%s]:[%d] FrameSize:%llu, offset:%llu, length:%llu ", __FUNCTION__, __LINE__,
4414 (unsigned long long)FrameBufferSize, (unsigned long long)*offset, (unsigned long long)*length);
4415 if (total_length < FrameBufferSize)
4416 {
4417 *offset = unUseSize;
4418 *length = total_length;
4419 }
4420 else // todo, dual decode case
4421 {
4422 *offset = unUseSize;
4423 *length = FrameBufferSize;
4424 }
4425 return TRUE;
4426 }
4427 #endif
4428
HAL_VPU_EX_strcmp(const char * string1,const char * string2)4429 static int HAL_VPU_EX_strcmp(const char *string1, const char *string2)
4430 {
4431 int iRet, i;
4432
4433 i = 0;
4434 while(string1[i] || string2[i])
4435 {
4436 iRet = string1[i] - string2[i];
4437 if(iRet)
4438 {
4439 return iRet;
4440 }
4441 i++;
4442 }
4443 return 0;
4444 }
4445
HAL_VPU_EX_GetCapability(MS_U8 * pu8CmdNameIn,void * pParamIn,void * pParamOut)4446 MS_BOOL HAL_VPU_EX_GetCapability(MS_U8 *pu8CmdNameIn, void *pParamIn, void *pParamOut)
4447 {
4448 typedef enum
4449 {
4450 E_CAP_NDEC_FB_MIU_SELECT,
4451 E_CAP_NDEC_NSTREAM_FB_SIZE,
4452 E_CAP_NDEC_NSTREAM_BS_SIZE,
4453 E_CAP_NDEC_SUPPORT_SHAREBBU,
4454 E_CAP_SUPPORT_ALLOCATOR,
4455
4456 } VPU_EX_GetCapabilityCmdId;
4457
4458 typedef struct
4459 {
4460 MS_U8 u8CmdId;
4461 MS_U8 u8CmdName[32];
4462
4463 } VPU_EX_GetCapabilityCmd;
4464
4465 static VPU_EX_GetCapabilityCmd stCapCmd[] =
4466 {
4467 {E_CAP_NDEC_FB_MIU_SELECT, "CAP_NDEC_FB_MIU_SELECT"},
4468 {E_CAP_NDEC_NSTREAM_FB_SIZE, "CAP_NDEC_NSTREAM_FB_SIZE"},
4469 {E_CAP_NDEC_NSTREAM_BS_SIZE, "CAP_NDEC_NSTREAM_BS_SIZE"},
4470 {E_CAP_NDEC_SUPPORT_SHAREBBU, "CAP_NDEC_SUPPORT_SHAREBBU"},
4471 {E_CAP_SUPPORT_ALLOCATOR, "CAP_SUPPORT_ALLOCATOR"},
4472 };
4473
4474 MS_U32 bRet = FALSE;
4475 MS_U32 u32TotalCmdCnt = sizeof(stCapCmd) / sizeof(stCapCmd[0]);
4476 MS_U32 u32CmdCnt;
4477
4478 for(u32CmdCnt = 0; u32CmdCnt < u32TotalCmdCnt; u32CmdCnt++)
4479 {
4480 if(HAL_VPU_EX_strcmp((const char *)(stCapCmd[u32CmdCnt].u8CmdName), (const char *)pu8CmdNameIn) == 0)
4481 {
4482 bRet = TRUE;
4483 switch(stCapCmd[u32CmdCnt].u8CmdId)
4484 {
4485 case E_CAP_NDEC_FB_MIU_SELECT:
4486 {
4487 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
4488 *pSupport = FALSE;
4489 }
4490 break;
4491
4492 // FIXME: Patch for waiting dynamic frame buffer and preset task_spec
4493 case E_CAP_NDEC_NSTREAM_FB_SIZE:
4494 {
4495 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
4496 *pSize = 0;
4497 }
4498 break;
4499
4500 // FIXME: Patch for waiting dynamic bitstream buffer
4501 case E_CAP_NDEC_NSTREAM_BS_SIZE:
4502 {
4503 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
4504 *pSize = 0;
4505 }
4506 break;
4507
4508 case E_CAP_NDEC_SUPPORT_SHAREBBU:
4509 {
4510 MS_BOOL *pbSupportShareBBU = (MS_BOOL *)pParamOut;
4511 *pbSupportShareBBU = FALSE;
4512 }
4513 break;
4514
4515 case E_CAP_SUPPORT_ALLOCATOR:
4516 {
4517 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
4518 *pSupport = FALSE;
4519 }
4520 break;
4521
4522 default:
4523 bRet = FALSE;
4524 break;
4525 }
4526 }
4527 }
4528
4529 return bRet;
4530 }
4531
4532 #else
4533 #include "halVPU_EX.h"
4534 #include "drvMMIO.h"
4535 #include "../hvd_v3/regHVD_EX.h"
4536 #include "halCHIP.h"
4537
4538 #if defined(MSOS_TYPE_NUTTX)
4539 extern int lib_lowprintf(const char *fmt, ...);
4540 #define PRINTF lib_lowprintf
4541 #elif defined(MSOS_TYPE_OPTEE)
4542 #define PRINTF printf
4543 #endif
4544
4545 #define HVD_LWORD(x) (MS_U16)((x)&0xffff)
4546 #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff)
4547
4548 MS_U8 u8FW_Binary[] = {
4549 #include "fwVPU.dat"
4550 };
4551
4552 MS_U32 u32HVDRegOSBase;
4553
HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)4554 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)
4555 {
4556 //PRINTF("do load code,u32DestAddr %x\n",addr);
4557 memcpy((void*)addr, (void*)u8FW_Binary, sizeof(u8FW_Binary));
4558 MAsm_CPU_Sync();
4559 MsOS_FlushMemory();
4560
4561 if (FALSE == (*((MS_U8*)(addr+6))=='R' && *((MS_U8*)(addr+7))=='2'))
4562 {
4563 PRINTF("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(addr+6), *(MS_U8*)(addr+7));
4564 return FALSE;
4565 }
4566 return TRUE;
4567 }
4568
HAL_VPU_EX_SetLockDownRegister(void * param)4569 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param)
4570 {
4571 #if 1
4572 MS_PHY u32StAddr_main;
4573 MS_PHY u32StAddr_sub;
4574 MS_U32 u32NonPMBankSize = 0;
4575 VPU_EX_LOCK_DOWN_REGISTER* register_lockdown;
4576
4577 if(param == NULL)
4578 {
4579 return FALSE;
4580 }
4581
4582 register_lockdown = (VPU_EX_LOCK_DOWN_REGISTER*)param;
4583
4584 MDrv_MMIO_GetBASE(&u32HVDRegOSBase, &u32NonPMBankSize, MS_MODULE_HW);
4585
4586 // ES buffer
4587 u32StAddr_main = register_lockdown->Bitstream_Addr_Main;
4588 u32StAddr_sub = register_lockdown->Bitstream_Addr_Sub;
4589
4590 if (u32StAddr_main >= register_lockdown->MIU1_BaseAddr)
4591 {
4592 u32StAddr_main -= register_lockdown->MIU1_BaseAddr;
4593 }
4594
4595 if (u32StAddr_sub >= register_lockdown->MIU1_BaseAddr)
4596 {
4597 u32StAddr_sub -= register_lockdown->MIU1_BaseAddr;
4598 }
4599
4600 //Lock down register
4601 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(REG_HVD_BASE), HVD_LWORD(u32StAddr_main >> 3));
4602 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(REG_HVD_BASE), HVD_HWORD(u32StAddr_main >> 3));
4603
4604 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(REG_HVD_BASE), HVD_LWORD(u32StAddr_sub >> 3));
4605 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(REG_HVD_BASE), HVD_HWORD(u32StAddr_sub >> 3));
4606 //~
4607
4608 // Lock Down
4609 //_HVD_Write2Byte(HVD_REG_HI_DUMMY_0, (_HVD_Read2Byte(HVD_REG_HI_DUMMY_0) | (HVD_REG_LOCK_REG_ESB_ST_ADR_L_H|HVD_REG_LOCK_REG_ESB_ST_ADR_L_H_BS2)));
4610 //~
4611 #endif
4612 return TRUE;
4613 }
4614
4615
4616 #endif
4617
4618