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Searched refs:_HVD_WriteRegBit (Results 1 – 25 of 68) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DhalHVD_EX.c212 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(6))
213 #define _MaskMiuReq_MVD_RW_RTO( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(1))
214 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(2))
215 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
216 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(5))
217 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(3))
219 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(6))
220 #define _MaskMiu1Req_MVD_RW_RTO( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK+1, m, BIT(1))
221 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(2))
222 #define _MaskMiu1Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(4))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DhalHVD_EX.c216 #define _MaskMiuReq_MVD_RW_0( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
217 #define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
218 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
219 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
220 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
221 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
223 #define _MaskMiu1Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
224 #define _MaskMiu1Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(6))
225 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
226 #define _MaskMiu1Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(2))
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DhalHVD_EX.c202 #define _MaskMiuReq_MVD_RW_0( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
203 #define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
204 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
205 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
206 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
207 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
209 #define _MaskMiu1Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
210 #define _MaskMiu1Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(6))
211 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
212 #define _MaskMiu1Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(2))
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DhalHVD_EX.c217 #define _MaskMiuReq_MVD_RW_0( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
218 #define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
219 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
220 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
221 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
222 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
224 #define _MaskMiu1Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
225 #define _MaskMiu1Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(6))
226 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
227 #define _MaskMiu1Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(2))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DhalHVD_EX.c216 #define _MaskMiuReq_MVD_RW_0( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
217 #define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
218 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
219 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
220 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
221 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
223 #define _MaskMiu1Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
224 #define _MaskMiu1Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(6))
225 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
226 #define _MaskMiu1Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(2))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/hvd/
H A DhalHVD_sub.c199 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(4))
200 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
201 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(2))
202 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1))
204 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(4))
205 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
206 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(2))
207 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1))
H A DhalHVD.c204 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
205 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
206 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
207 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(1))
209 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
210 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
211 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
212 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(1))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/hvd/
H A DhalHVD_sub.c199 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(4))
200 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
201 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(2))
202 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1))
204 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(4))
205 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
206 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(2))
207 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1))
H A DhalHVD.c204 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
205 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
206 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
207 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(1))
209 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
210 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
211 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
212 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(1))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/hvd/
H A DhalHVD_sub.c199 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(4))
200 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
201 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(2))
202 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1))
204 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(4))
205 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
206 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(2))
207 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/hvd/
H A DhalHVD_sub.c199 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(4))
200 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
201 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(2))
202 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1))
204 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(4))
205 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
206 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(2))
207 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1))
H A DhalHVD.c204 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
205 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
206 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
207 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(1))
209 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
210 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
211 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
212 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(1))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/hvd/
H A DhalHVD_sub.c199 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(4))
200 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
201 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(2))
202 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1))
204 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(4))
205 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
206 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(2))
207 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/hvd/
H A DhalHVD_sub.c199 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(4))
200 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
201 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(2))
202 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1))
204 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(4))
205 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
206 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(2))
207 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1))
H A DhalHVD.c204 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
205 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
206 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
207 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(1))
209 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
210 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
211 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
212 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/hvd_ex/
H A DhalHVD_EX.c196 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
197 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
198 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
199 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(1))
201 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
202 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
203 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
204 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(1))
212 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(5))
213 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(4))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/hvd_ex/
H A DhalHVD_EX.c196 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(4))
197 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
198 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(2))
199 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1))
201 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(4))
202 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
203 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(2))
204 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1))
212 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
213 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(3))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/hvd_ex/
H A DhalHVD_EX.c196 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
197 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
198 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
199 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(1))
201 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
202 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
203 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
204 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(1))
212 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(5))
213 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(4))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/hvd_ex/
H A DhalHVD_EX.c196 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
197 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
198 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
199 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(1))
201 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
202 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
203 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
204 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(1))
212 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(5))
213 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(4))
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/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/hvd_ex/
H A DhalHVD_EX.c196 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(4))
197 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
198 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(2))
199 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1))
201 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(4))
202 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
203 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(2))
204 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1))
212 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
213 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(3))
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/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/hvd_ex/
H A DhalHVD_EX.c196 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
197 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
198 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
199 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(1))
201 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
202 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
203 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
204 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(1))
212 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(5))
213 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(4))
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/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/hvd_ex/
H A DhalHVD_EX.c196 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
197 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
198 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
199 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(1))
201 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
202 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
203 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
204 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(1))
212 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(5))
213 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(4))
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/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/hvd_ex/
H A DhalHVD_EX.c196 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
197 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
198 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
199 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(1))
201 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
202 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
203 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
204 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(1))
212 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(5))
213 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(4))
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/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/hvd_ex/
H A DhalHVD_EX.c196 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
197 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
198 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
199 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(1))
201 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
202 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
203 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
204 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(1))
212 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(5))
213 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(4))
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/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/hvd_ex/
H A DhalHVD_EX.c196 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
197 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
198 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
199 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(1))
201 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
202 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
203 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
204 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(1))
212 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(5))
213 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK+1, m, BIT(4))
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