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Searched refs:VDEC_STR_BUFFER_START (Results 1 – 25 of 25) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/vpu_ex/
H A Dcontroller.h160 #define VDEC_STR_BUFFER_START 0x2B0000 macro
161 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
166 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
167 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
168 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
169 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
170 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
171 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
172 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
173 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/vpu_ex/
H A Dcontroller.h160 #define VDEC_STR_BUFFER_START 0x2B0000 macro
161 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
166 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
167 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
168 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
169 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
170 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
171 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
172 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
173 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/vpu_ex/
H A Dcontroller.h160 #define VDEC_STR_BUFFER_START 0x2B0000 macro
161 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
166 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
167 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
168 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
169 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
170 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
171 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
172 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
173 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/vpu_ex/
H A Dcontroller.h160 #define VDEC_STR_BUFFER_START 0x2B0000 macro
161 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
166 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
167 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
168 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
169 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
170 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
171 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
172 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
173 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/vpu_ex/
H A Dcontroller.h160 #define VDEC_STR_BUFFER_START 0x2B0000 macro
161 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
166 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
167 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
168 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
169 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
170 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
171 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
172 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
173 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/vpu_ex/
H A Dcontroller.h160 #define VDEC_STR_BUFFER_START 0x2B0000 macro
161 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
166 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
167 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
168 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
169 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
170 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
171 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
172 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
173 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/vpu_ex/
H A Dcontroller.h160 #define VDEC_STR_BUFFER_START 0x2B0000 macro
161 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
166 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
167 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
168 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
169 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
170 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
171 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
172 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
173 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/vpu_ex/
H A Dcontroller.h160 #define VDEC_STR_BUFFER_START 0x2B0000 macro
161 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
166 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
167 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
168 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
169 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
170 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
171 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
172 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
173 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/vpu_ex/
H A Dcontroller.h160 #define VDEC_STR_BUFFER_START 0x2B0000 macro
161 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
166 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
167 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
168 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
169 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
170 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
171 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
172 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
173 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/vpu_ex/
H A Dcontroller.h160 #define VDEC_STR_BUFFER_START 0x2B0000 macro
161 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
166 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
167 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
168 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
169 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
170 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
171 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
172 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
173 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A Dcontroller.h178 #define VDEC_STR_BUFFER_START 0x2B0000
179 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
184 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
185 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
186 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
187 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
188 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
189 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
190 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
191 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A Dcontroller.h205 #define VDEC_STR_BUFFER_START 0x2B0000
206 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
211 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
212 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
213 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
214 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
215 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
216 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
217 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
218 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maldives/vpu_v3/
H A Dcontroller.h300 #define VDEC_STR_BUFFER_START 0x2B0000
301 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
306 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
307 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
308 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
309 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
310 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
311 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
312 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
313 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A Dcontroller.h300 #define VDEC_STR_BUFFER_START 0x2B0000
301 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
306 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
307 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
308 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
309 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
310 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
311 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
312 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
313 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A Dcontroller.h300 #define VDEC_STR_BUFFER_START 0x2B0000
301 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
306 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
307 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
308 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
309 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
310 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
311 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
312 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
313 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/vpu_v3/
H A Dcontroller.h300 #define VDEC_STR_BUFFER_START 0x2B0000
301 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
306 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
307 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
308 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
309 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
310 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
311 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
312 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
313 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/vpu_v3/
H A Dcontroller.h300 #define VDEC_STR_BUFFER_START 0x2B0000
301 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
306 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
307 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
308 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
309 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
310 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
311 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
312 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
313 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/vpu_v3/
H A Dcontroller.h300 #define VDEC_STR_BUFFER_START 0x2B0000
301 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
306 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
307 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
308 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
309 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
310 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
311 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
312 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
313 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A Dcontroller.h300 #define VDEC_STR_BUFFER_START 0x2B0000
301 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
306 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
307 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
308 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
309 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
310 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
311 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
312 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
313 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/vpu_v3/
H A Dcontroller.h302 #define VDEC_STR_BUFFER_START 0x2B0000
303 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
308 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
309 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
310 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
311 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
312 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
313 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
314 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
315 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/vpu_v3/
H A Dcontroller.h302 #define VDEC_STR_BUFFER_START 0x2B0000
303 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
308 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
309 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
310 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
311 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
312 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
313 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
314 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
315 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A Dcontroller.h302 #define VDEC_STR_BUFFER_START 0x2B0000
303 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
308 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
309 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
310 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
311 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
312 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
313 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
314 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
315 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/vpu_v3/
H A Dcontroller.h302 #define VDEC_STR_BUFFER_START 0x2B0000
303 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
308 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
309 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
310 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
311 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
312 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
313 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
314 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
315 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/vpu_v3/
H A Dcontroller.h302 #define VDEC_STR_BUFFER_START 0x2B0000
303 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
308 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
309 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
310 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
311 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
312 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
313 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
314 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
315 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/
H A Dcontroller.h302 #define VDEC_STR_BUFFER_START 0x2B0000
303 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN)
308 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START
309 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1
310 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2
311 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3
312 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4
313 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5
314 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6
315 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE