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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _CONTROL_H_ 96 #define _CONTROL_H_ 97 98 extern void CTL_main( void *pvParameters ); 99 extern void CTL_Init(void); 100 extern void CTL_Deinit(void); 101 102 #define CTL_VERSION 0x14063017 103 #define CTL_INFO_ADDR 0x0 104 105 // _ctl_info statue 106 #define CTL_STU_NONE 0 107 #define CTL_STU_INIT 1 108 #define CTL_STU_TASK 2 109 110 // _ctl_info task_statue[x] 111 #define CTL_TASK_NONE 0 112 #define CTL_TASK_CREATE 1 // task has already created by controller 113 #define CTL_TASK_CMDRDY 2 // task has already inited and ready to get command 114 115 // _ctl_info task_mode 116 #define CTL_MODE_NORMAL 0 117 #define CTL_MODE_3DWMV 1 // 3d wmv 118 #define CTL_MODE_3DTV 2 // mpeg2+h.264 119 #define CTL_MODE_3DTV_PROG 3 // Korea 3DTV forced progressive mode 120 #define CTL_MODE_ONE_STC 4 // only one STC, sub view sync main stc 121 #define CTL_MODE_SWITCH_STC 5 // switch target STC , main view sync sub stc and sub view sync main stc 122 #define CTL_MODE_3DTV_TWO_PITCH 6 //Korea 3DTV, 2nd pitch enabled for 3DLR 123 #define CTL_MODE_3DTV_PROG_TWO_PITCH 7 // Korea 3DTV PROG, 2nd pitch enabled for 3DLR 124 #define CTL_MODE_SEC_MCU 8 125 126 //fw allocate dram 127 #if defined(SUPPORT_NEW_MEM_LAYOUT) 128 #define DRAM_OFFSET 0x20000 // starts from 0xB0000+0x20000 129 #elif (SUPPORT_EVD) // Local FPGA verification 130 #define DRAM_START 0x100000 131 #else //For HVD and MVD, or real chip verification 132 #define DRAM_START 0xA0000 133 #endif // #if defined(SUPPORT_NEW_MEM_LAYOUT) 134 135 #if defined(SUPPORT_NEW_MEM_LAYOUT) 136 #if defined(SUPPORT_EVD) && (SUPPORT_EVD==1) 137 #define HEAP_START 0xD0000 138 #else 139 #define HEAP_START 0xC0000 140 #endif 141 #else 142 #define HEAP_START 0xA0000 143 #endif 144 145 #define VSYNC_BRIDGE_OFFSET 0x1FA00 146 147 148 #if defined(SUPPORT_VDEC_STR) 149 /* 150 | STR_FLAG : 16byte | CTL_CMD : 15 set | MAIN_CMD : 120 set | SUB_CMD : 120 set | 151 152 1 set = 16 byte 153 total str buffer ~ 4k 154 */ 155 156 #define VDEC_STR_ALIGN 16 157 #define VDEC_STR_CTL_CMD_RESERVERD 8 158 #define VDEC_STR_CMD_RESERVERD 120 159 160 #define VDEC_STR_BUFFER_START 0x2B0000 161 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN) 162 #define VDEC_STR_SUB_CTL_CMD_BUF (VDEC_STR_MAIN_CTL_CMD_BUF + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 163 #define VDEC_STR_MAIN_CMD_BUF (VDEC_STR_SUB_CTL_CMD_BUF + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 164 #define VDEC_STR_SUB_CMD_BUF (VDEC_STR_MAIN_CMD_BUF + (VDEC_STR_ALIGN * VDEC_STR_CMD_RESERVERD)) 165 166 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START 167 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1 168 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2 169 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3 170 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4 171 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5 172 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6 173 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE 174 175 #define VDEC_STR_CMD 4 176 #define VDEC_STR_ARG0 8 177 #define VDEC_STR_ARG1 9 178 #define VDEC_STR_ARG2 10 179 #define VDEC_STR_ARG3 11 180 #define VDEC_STR_ARG4 12 181 #define VDEC_STR_ARG5 13 182 183 #define VDEC_STR_MVD 1 184 #define VDEC_STR_HVD 2 185 186 #define VDEC_UNMUTE_BYTE 7 187 188 #endif 189 /* Structure defination */ 190 struct _ctl_info { 191 const unsigned int readonly[4]; // CTL_INFO_ADDR + 0x00 read only for tag. 192 unsigned int vpu_clk; // CTL_INFO_ADDR + 0x10 reserved for driver to fw message.(VDEC CPU clock) 193 unsigned int ctl_interface; // CTL_INFO_ADDR + 0x14 driver interface(read only) 194 unsigned int heap_size[2]; // CTL_INFO_ADDR + 0x18 heap size available for each task 195 unsigned int verion; // CTL_INFO_ADDR + 0x20 196 unsigned int statue; // CTL_INFO_ADDR + 0x24 197 unsigned int last_ctl_cmd; // CTL_INFO_ADDR + 0x28 198 unsigned int last_ctl_arg; // CTL_INFO_ADDR + 0x2C 199 unsigned int task_statue[4]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment 200 unsigned int task_single; // CTL_INFO_ADDR + 0x40 201 unsigned short task_mode[2]; // CTL_INFO_ADDR + 0x44 0:normal 1:3d WMV 2:korea 3d TV 202 unsigned int burst_mode; // CTL_INFO_ADDR + 0x48 0:normal 1:burst cmd 203 unsigned char task_hvd; // CTL_INFO_ADDR + 0x4c 204 unsigned char task_mvd; // CTL_INFO_ADDR + 0x4d 205 unsigned short u16TaskFeature; // CTL_INFO_ADDR + 0x4e 206 unsigned int u32Reserved; // CTL_INFO_ADDR + 0x50 reserved 207 unsigned int u32TaskShareInfoAddr[4]; // CTL_INFO_ADDR + 0x54 offset from FW beginning 208 unsigned int u32VsyncBridgeAddr; // CTL_INFO_ADDR + 0x64 209 unsigned int FB_ADDRESS; // CTL_INFO_ADDR + 0x68 , this value is offset of miu, unit is byte 210 unsigned int FB_Total_SIZE; // CTL_INFO_ADDR + 0x6C , unit is byte 211 unsigned int FB_Used_SIZE; // CTL_INFO_ADDR + 0x70 , unit is byte 212 } ; 213 214 215 extern struct _ctl_info *g_ctl_ptr; 216 extern unsigned char Wakeup_Controller(unsigned char ISR); 217 extern unsigned char CTL_burst_cmd(unsigned int cmd, unsigned int arg); 218 219 220 221 #endif // _CONTROL_H_ 222 223