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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _CONTROL_H_ 96 #define _CONTROL_H_ 97 98 extern void CTL_main( void *pvParameters ); 99 extern void CTL_Init(void); 100 extern void CTL_Deinit(void); 101 102 #define CTL_VERSION 0x18012418 103 #define CTL_INFO_ADDR 0x0 104 105 // _ctl_info statue 106 #define CTL_STU_NONE 0 107 #define CTL_STU_INIT 1 108 #define CTL_STU_TASK 2 109 110 // _ctl_info task_statue[x] 111 #define CTL_TASK_NONE 0 112 #define CTL_TASK_CREATE 1 // task has already created by controller 113 #define CTL_TASK_CMDRDY 2 // task has already inited and ready to get command 114 #define CTL_TASK_TO_BE_DELETED 3 // task is going to be deteled 115 #define CTL_TASK_CMD 4 116 117 #define VDEC_TAG 0xFE 118 #define MVD_DECODER 1 119 #define HVD_DECODER 2 120 121 122 // _ctl_info task_mode 123 #define CTL_MODE_NORMAL 0 124 #define CTL_MODE_3DWMV 1 // 3d wmv 125 #define CTL_MODE_3DTV 2 // mpeg2+h.264 126 #define CTL_MODE_3DTV_PROG 3 // Korea 3DTV forced progressive mode 127 #define CTL_MODE_ONE_STC 4 // only one STC, sub view sync main stc 128 #define CTL_MODE_SWITCH_STC 5 // switch target STC , main view sync sub stc and sub view sync main stc 129 #define CTL_MODE_3DTV_TWO_PITCH 6 //Korea 3DTV, 2nd pitch enabled for 3DLR 130 #define CTL_MODE_3DTV_PROG_TWO_PITCH 7 // Korea 3DTV PROG, 2nd pitch enabled for 3DLR 131 #define CTL_MODE_SEC_MCU 8 132 133 #define MAX_TASKS 16 // max tasks number 134 #define VSYNC_BRIDGE_TASK_NUM 4 135 136 #define VDEC_FW31 137 #define VDEC_FW31_HVD_NONAUTO_BBU 138 139 #ifdef LIGHTWEIGHT //FW31_1.8M 140 #define COMMON_AREA_START 0xB0000 141 #define HEAP_START 0xE0000 142 #else 143 #if defined(SUPPORT_EVD) && (SUPPORT_EVD==1) 144 #define COMMON_AREA_START 0xF0000 145 #define HEAP_START 0x130000 146 #else 147 #define COMMON_AREA_START 0x90000 148 #define HEAP_START 0xC0000 149 #endif 150 #endif 151 152 #define INSIDE_SHM_SIZE 0x200 153 #define INSIDE_SHM_START (COMMON_AREA_START-INSIDE_SHM_SIZE) 154 //#define SW_MFC_DEC // use S/W MFCodec to decode if defined. Otherwise calculate the MD5 of mfcoded rec data. 155 156 typedef enum 157 { 158 E_CTL_IQMEM_INIT_NONE = 0, 159 E_CTL_IQMEM_INIT_LOADING, //HK -> FW 160 E_CTL_IQMEM_INIT_LOADED, //FW -> HK 161 E_CTL_IQMEM_INIT_FINISH //HK -> FW 162 } CTL_IQMEM_INIT_STATUS; 163 164 typedef enum 165 { 166 E_CTL_DISPLAY_PATH_MVOP_0 = 0, 167 E_CTL_DISPLAY_PATH_MVOP_1, 168 E_CTL_DISPLAY_PATH_MVOP_MAX, 169 E_CTL_DISPLAY_PATH_NONE = 0xff, //display by DIP 170 } CTL_DISPLAY_PATH; 171 172 typedef enum 173 { 174 E_CTL_INPUT_TSP_0 = 0, 175 E_CTL_INPUT_TSP_1 = 1, 176 E_CTL_INPUT_TSP_2 = 2, 177 E_CTL_INPUT_TSP_3 = 3, 178 E_CTL_INPUT_TSP_MAX = 4, 179 E_CTL_INPUT_TSP_NONE = 0xFF, 180 } CTL_INPUT_TSP; 181 182 typedef enum 183 { 184 E_CTL_HDMI_POLICY_NONE = 0, 185 E_CTL_HDMI_POLICY_BLUESCREEN = 1, 186 E_CTL_HDMI_POLICY_SD = 2, 187 E_CTL_HDMI_POLICY_HD = 3, 188 E_CTL_HDMI_POLICY_FHD = 4, 189 E_CTL_HDMI_POLICY_4K = 5, 190 } CTL_HDMI_POLICY; 191 192 193 194 #if 1 195 /* 196 == Common Area Layout == 197 198 +-----------------------------------+ 0x0 199 | HVD_BBU_TBL_SIZE * 4 | 200 +-----------------------------------+ 0x4000 201 | EVD_BBU_TBL_SIZE * 4 | 202 +-----------------------------------+ 0x8000 203 | VP8_BBU_TBL_SIZE * 2 | 204 +-----------------------------------+ 0xA000 205 | MVD_SLQ_TBL_SIZE * 4 | 206 +-----------------------------------+ 0xC000 207 | VSyncBridge structure * 2 | 208 | ds_xc_data_structure (old usage) | 209 +-----------------------------------+ 0xC800 210 | VSyncBridgeExt structure * 2 | 211 +-----------------------------------+ 0xD000 212 | VSyncBridge structure * 2 | 213 +-----------------------------------+ 0xD800 214 | VSyncBridgeExt structure * 2 | 215 +-----------------------------------+ 0xE000 216 | DS IP OP Page | 217 +-----------------------------------+ 0xFF00 218 | DS Scaler Info | 219 +-----------------------------------+ 0x10000 220 221 */ 222 223 #define HVD_BBU_TBL_SIZE 0x1000 224 #define EVD_BBU_TBL_SIZE 0x1000 225 #define VP8_BBU_TBL_SIZE 0x1000 226 #define MVD_SLQ_TBL_SIZE 0x800 227 #define VSYNC_BRIDGE_INFO_SIZE 0x400 228 229 #define HVD_BBU_TBL_OFFSET 0x0 230 #define EVD_BBU_TBL_OFFSET 0x4000 231 #define VP8_BBU_TBL_OFFSET 0x8000 232 #define MVD_SLQ_TBL_OFFSET 0xA000 233 #define VSYNC_BRIDGE_OFFSET 0xC000 // 2 * sizeof(MCU_DISPQ_INFO) + sizeof(ds_xc_data_structure) 234 #define VSYNC_BRIDGE_EXT_OFFSET 0xC800 // 2 * sizeof(MCU_DISPQ_INFO_EXT) 235 #define VSYNC_BRIDGE_NWAY_OFFSET 0xD000 // 2 MCU_DISPQ_INFO, each occupy 0x400 236 #define VSYNC_BRIDGE_EXT_NWAY_OFFSET 0xD800 // 2 MCU_DISPQ_INFO_EXT, each occupy 0x400 237 #define DS_IPOP_PAGE_OFFSET 0xE000 238 #define DS_SCALER_INFO_OFFSET 0xFF00 //0x10F00 239 #else 240 /* 241 == Common Area Layout == 242 243 +-----------------------------------+ 0x0 244 | HVD_BBU_TBL_SIZE * 4 | 245 +-----------------------------------+ 0x4000 246 | EVD_BBU_TBL_SIZE * 4 | 247 +-----------------------------------+ 0x5000 248 | VP8_BBU_TBL_SIZE * 2 | 249 +-----------------------------------+ 0x5800 250 | MVD_SLQ_TBL_SIZE * 4 | 251 +-----------------------------------+ 0x6000 252 | VSyncBridge structure * 2 | 253 | ds_xc_data_structure (old usage) | 254 +-----------------------------------+ 0x6800 255 | VSyncBridgeExt structure * 2 | 256 +-----------------------------------+ 0x7000 257 | VSyncBridge structure * 2 | 258 +-----------------------------------+ 0x7800 259 | VSyncBridgeExt structure * 2 | 260 +-----------------------------------+ 0x8000 261 | DS IP OP Page | 262 +-----------------------------------+ 0x9F00 263 | DS Scaler Info | 264 +-----------------------------------+ 0xA000 265 266 */ 267 268 #define HVD_BBU_TBL_SIZE 0x1000 269 #define EVD_BBU_TBL_SIZE 0x400 270 #define VP8_BBU_TBL_SIZE 0x400 271 #define MVD_SLQ_TBL_SIZE 0x200 272 #define VSYNC_BRIDGE_INFO_SIZE 0x400 273 274 #define HVD_BBU_TBL_OFFSET 0x0 275 #define EVD_BBU_TBL_OFFSET 0x4000 276 #define VP8_BBU_TBL_OFFSET 0x5000 277 #define MVD_SLQ_TBL_OFFSET 0x5800 278 #define VSYNC_BRIDGE_OFFSET 0x6000 279 #define VSYNC_BRIDGE_EXT_OFFSET 0x6800 280 #define VSYNC_BRIDGE_NWAY_OFFSET 0x7000 281 #define VSYNC_BRIDGE_EXT_NWAY_OFFSET 0x7800 282 #define DS_IPOP_PAGE_OFFSET 0x8000 283 #define DS_SCALER_INFO_OFFSET 0x9F00 284 #endif 285 286 #define COMMON_AREA_SIZE 0x10000 287 #define FW_TASK_SIZE 0x100000 288 289 #if defined(SUPPORT_VDEC_STR) 290 /* 291 | STR_FLAG : 16byte | CTL_CMD : 15 set | MAIN_CMD : 120 set | SUB_CMD : 120 set | 292 293 1 set = 16 byte 294 total str buffer ~ 4k 295 */ 296 297 #define VDEC_STR_ALIGN 16 298 #define VDEC_STR_CTL_CMD_RESERVERD 8 299 #define VDEC_STR_CMD_RESERVERD 120 300 301 #if 0 302 #define VDEC_STR_BUFFER_START 0x2B0000 303 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN) 304 #define VDEC_STR_SUB_CTL_CMD_BUF (VDEC_STR_MAIN_CTL_CMD_BUF + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 305 #define VDEC_STR_MAIN_CMD_BUF (VDEC_STR_SUB_CTL_CMD_BUF + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 306 #define VDEC_STR_SUB_CMD_BUF (VDEC_STR_MAIN_CMD_BUF + (VDEC_STR_ALIGN * VDEC_STR_CMD_RESERVERD)) 307 308 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START 309 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1 310 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2 311 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3 312 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4 313 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5 314 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6 315 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE 316 #else 317 318 #define VDEC_STR_BUFFER_DUAL_OFFSET 0x2B0000 319 #define VDEC_STR_BUFFER_SINGLE_OFFSET 0x1D0000 320 321 #define VDEC_STR_MAIN_CTL_CMD_OFFSET (VDEC_STR_ALIGN) 322 #define VDEC_STR_SUB_CTL_CMD_OFFSET (VDEC_STR_MAIN_CTL_CMD_OFFSET + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 323 #define VDEC_STR_MAIN_CMD_OFFSET (VDEC_STR_SUB_CTL_CMD_OFFSET + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 324 #define VDEC_STR_SUB_CMD_OFFSET (VDEC_STR_MAIN_CMD_OFFSET + (VDEC_STR_ALIGN * VDEC_STR_CMD_RESERVERD)) 325 326 #define VDEC_STR_MAIN_WORK_OFFSET 0x0 327 #define VDEC_STR_SUB_WORK_OFFSET 0x1 328 #define VDEC_STR_MAIN_RESUME_OFFSET 0x2 329 #define VDEC_STR_SUB_RESUME_OFFSET 0x3 330 #define VDEC_STR_MAIN_CTL_CMD_COUNT_OFFSET 0x4 331 #define VDEC_STR_SUB_CTL_CMD_COUNT_OFFSET 0x5 332 #define VDEC_STR_MAIN_CMD_COUNT_OFFSET 0x6 333 #define VDEC_STR_SUB_CMD_COUNT_OFFSET 0x8 //0x7 for VDEC_UNMUTE_BYTE 334 335 #endif 336 337 338 339 #define VDEC_STR_CMD 4 340 #define VDEC_STR_ARG0 8 341 #define VDEC_STR_ARG1 9 342 #define VDEC_STR_ARG2 10 343 #define VDEC_STR_ARG3 11 344 #define VDEC_STR_ARG4 12 345 #define VDEC_STR_ARG5 13 346 347 #define VDEC_STR_MVD 1 348 #define VDEC_STR_HVD 2 349 350 #define VDEC_UNMUTE_BYTE 7 351 352 #endif 353 /* Structure definition */ 354 struct _ctl_info { 355 const unsigned int readonly[4]; // CTL_INFO_ADDR + 0x00 read only for tag. 356 unsigned int vpu_clk; // CTL_INFO_ADDR + 0x10 reserved for driver to fw message.(VDEC CPU clock) 357 unsigned int ctl_interface; // CTL_INFO_ADDR + 0x14 driver interface(read only) 358 unsigned int verion; // CTL_INFO_ADDR + 0x18 359 unsigned int statue; // CTL_INFO_ADDR + 0x1C 360 unsigned int last_ctl_cmd; // CTL_INFO_ADDR + 0x20 361 unsigned int last_ctl_arg; // CTL_INFO_ADDR + 0x24 362 unsigned short task_single; // CTL_INFO_ADDR + 0x28 363 unsigned short burst_mode; // CTL_INFO_ADDR + 0x2A 0:normal 1:burst cmd 364 unsigned char task_hvd; // CTL_INFO_ADDR + 0x2C 365 unsigned char task_mvd; // CTL_INFO_ADDR + 0x2D 366 unsigned char task_evd; // CTL_INFO_ADDR + 0x2E 367 unsigned char u8TaskFeature; // CTL_INFO_ADDR + 0x2F 368 369 unsigned char task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment 370 unsigned char task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x40 0:normal 1:3d WMV 2:korea 3d TV 371 unsigned int u32TaskShareInfoAddr[MAX_TASKS]; // CTL_INFO_ADDR + 0x50 offset from FW beginning 372 373 unsigned int u32CommonAreaAddr; // CTL_INFO_ADDR + 0x90 374 375 unsigned int FB_ADDRESS; // CTL_INFO_ADDR + 0x94 , this value is offset of miu, unit is byte 376 unsigned int FB_Total_SIZE; // CTL_INFO_ADDR + 0x98 , unit is byte 377 unsigned int FB_Used_SIZE; // CTL_INFO_ADDR + 0x9C , unit is byte 378 unsigned int u32FrameBufAddr; // CTL_INFO_ADDR + 0xA0 frame buffer base address 379 unsigned int u32FrameBufSize; // CTL_INFO_ADDR + 0xA4 frame buffer size for all tasks 380 unsigned char u8FrameBufSegment; // CTL_INFO_ADDR + 0xA8 select one enumeration from Split_FB 381 unsigned char bFrameBufUsed[4]; // CTL_INFO_ADDR + 0xA9 record if each segment is used. 382 unsigned char u8UseIMITaskId; // CTL_INFO_ADDR + 0xAD indicate which task is using IMI 383 unsigned char u8HicodecType; // CTL_INFO_ADDR + 0xAE Kano, 0:Hicodec 1:Hicodec_Lite 384 unsigned char bEnableHvdNonAutoBBU; // CTL_INFO_ADDR + 0xAF 385 unsigned int u32DolbyVisionXCShmAddr; // CTL_INFO_ADDR + 0xB0 record the dolby vision XC share memory address for transfer DM/composer 386 unsigned int u32Reserved; // CTL_INFO_ADDR + 0xB4 387 unsigned char u8STCIndex[MAX_TASKS]; // CTL_INFO_ADDR + 0xB8 388 volatile unsigned char u8IQmemCtrl; // CTL_INFO_ADDR + 0xC8 389 unsigned char bIsIQMEMSupport; // CTL_INFO_ADDR + 0xC9 390 unsigned char bIQmemEnableIfSupport; // CTL_INFO_ADDR + 0xCA 391 unsigned char bReserved; // CTL_INFO_ADDR + 0xCB 392 #if defined(SUPPORT_VDEC_STR) 393 unsigned int u32StrAddrOffset; // CTL_INFO_ADDR + 0xCC 394 #endif 395 } ; 396 397 #define INVALID_ADDR_U32 0xFFFFFFFF 398 399 #define VDEC_SHARE_MEM_MASK 0x0FFFFFFF 400 #define VDEC_BBU_ID_MASK 0xF0000000 401 #define VDEC_BBU_ID_SHIFT 28 402 403 #define MAX_VDEC_VBBU_ENTRY_COUNT 254 404 405 typedef struct 406 { 407 unsigned int u32Offset; ///< Packet offset from bitstream buffer base address. unit: byte. 408 unsigned int u32Length; ///< Packet size. unit: byte. ==> Move _VDEC_EX_ReparseVP8Packet to FW 409 unsigned long long u64TimeStamp; ///< Packet time stamp. 410 unsigned int u32ID_L; ///< Packet ID low part. 411 unsigned int u32ID_H; ///< Packet ID high part. 412 unsigned char u8Version; ///< 0 means u32Offset is the offset of ES buffer 413 ///< 1 means u32Offset is used as esHandleID 414 unsigned char u8Reserved[7]; ///< Revserved space and for 16-byte alignment 415 } VDEC_VBBU_Entry; 416 417 typedef struct 418 { 419 unsigned int u32WrPtr; 420 unsigned int u32RdPtr; 421 unsigned char u8Reserved[8]; 422 VDEC_VBBU_Entry stEntry[MAX_VDEC_VBBU_ENTRY_COUNT + 1]; 423 } VDEC_VBBU; 424 425 typedef struct 426 { 427 unsigned int u32Offset; ///< Packet offset from bitstream buffer base address. unit: byte. 428 unsigned int u32Length; ///< Packet size. unit: byte. 429 } VDEC_ESMap_Entry; 430 431 typedef struct 432 { 433 unsigned int u32WrPtr; 434 unsigned int u32RdPtr; 435 VDEC_ESMap_Entry stEntry[MAX_VDEC_VBBU_ENTRY_COUNT + 1]; 436 } VDEC_ESMap_Table; 437 438 typedef struct 439 { 440 unsigned int u32HVD_PENDING_RELEASE_ST_ADDR;//[0][0]:0x0D98 [0][1]:0x0DA4 [1][0]:0x0DB0 [1][1]:0x0DBC 441 unsigned int u32HVD_PENDING_RELEASE_SIZE; //[0][0]:0x0D9C [0][1]:0x0DA8 [1][0]:0x0DB4 [1][1]:0x0DC0 442 unsigned int u32HVD_COLLISION_NUM; //[0][0]:0x0DA0 [0][1]:0x0DAC [1][0]:0x0DB8 [1][1]:0x0DC4 443 } PENDING_RELEASE_QUEUE; 444 445 typedef struct 446 { 447 unsigned int u32HVD_DISPCMDQ_DRAM_ST_ADDR;//0x0FA8 // for VDEC3 display command queue usage 448 unsigned int u32HVD_STREAM_DISPCMDQ_RD; //0x0FAC // stream display command queue read ptr for VDEC3 display command queue usage 449 unsigned int u32HVD_STREAM_DISPCMDQ_WD; //0x0FB0 // stream display command queue write ptr for VDEC3 display command queue usage 450 unsigned int u32HVD_CMDQ_DRAM_ST_ADDR; //0x0FB4 // for VDEC3 dram command queue usage 451 unsigned int u32HVD_STREAM_CMDQ_RD; //0x0FB8 // stream command queue read ptr for VDEC3 dram command queue usage 452 unsigned int u32HVD_STREAM_CMDQ_WD; //0x0FBC // stream command queue write ptr for VDEC3 dram command queue usage 453 } CMD_QUEUE; 454 455 typedef struct 456 { 457 unsigned int u32FrameBufAddr; // For main Frame Buffer 458 unsigned int u32FrameBufSize; // For main Frame Buffer 459 unsigned int u32FrameBuf2Addr; // For Balance Frame Buffer 460 unsigned int u32FrameBuf2Size; // For Balance Frame Buffer 461 unsigned char u8FrameBufMiuSel; // For main Frame Buffer 462 unsigned char u8FrameBuf2MiuSel; // For Balance Frame Buffer 463 unsigned short u16Reserved; // Reserved for frame buffer address over 4G 464 } VDEC_INSIDE_FRM_BUF_INFO; 465 466 typedef struct 467 { 468 unsigned char u8code[16];//for magic number 469 unsigned char u8MaxTaskNum; // current==2 470 unsigned char u8Resv[1]; 471 unsigned char u8HDMIPolicyVer; /// HDMI policy version info 472 unsigned char u8HDMIPolicyCnt; /// HDMI policy update count 473 // 32 24 16 8 0 474 // +-----+-----+-----+-----+ 475 // |8bits|8bits|8bits|8bits| 476 // +-----+-----+-----+-----+ 477 // | 4K | FHD | HD | SD | 478 // +-----+-----+-----+-----+ 479 unsigned int u32HDMIPolicyInfo; /// HDMI policy infomation 480 unsigned int u32Resv[31]; 481 VDEC_INSIDE_FRM_BUF_INFO stINSIDE_SHM[2]; 482 } VDEC_INSIDE_SHM; 483 484 extern struct _ctl_info *g_ctl_ptr; 485 extern unsigned char Wakeup_Controller(unsigned char ISR); 486 extern unsigned char CTL_burst_cmd(unsigned int cmd, unsigned int arg); 487 488 #if defined(_WIN32) || defined(_LINUX_X64_) 489 extern volatile char g_ctl_Version[]; 490 #else 491 extern volatile char g_ctl_Version[] __attribute__ ((section(".tail_version"), aligned(16))); 492 #endif 493 494 495 #if defined(_WIN32) || defined(_LINUX_X64_) 496 void CTL_lock(void); 497 void CTL_unlock(void); 498 int CTL_Set_DRV_Cmd(unsigned char id, unsigned int cmd, unsigned int arg); 499 char *CTL_get_mem_pool_ptr(void); 500 #endif 501 502 #endif // _CONTROL_H_ 503 504