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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _CONTROL_H_ 96 #define _CONTROL_H_ 97 98 extern void CTL_main( void *pvParameters ); 99 extern void CTL_Init(void); 100 extern void CTL_Deinit(void); 101 102 #define CTL_VERSION 0x16121409 103 #define CTL_INFO_ADDR 0x0 104 105 // _ctl_info statue 106 #define CTL_STU_NONE 0 107 #define CTL_STU_INIT 1 108 #define CTL_STU_TASK 2 109 110 // _ctl_info task_statue[x] 111 #define CTL_TASK_NONE 0 112 #define CTL_TASK_CREATE 1 // task has already created by controller 113 #define CTL_TASK_CMDRDY 2 // task has already inited and ready to get command 114 #define CTL_TASK_TO_BE_DELETED 3 // task is going to be deteled 115 #define CTL_TASK_CMD 4 116 117 #define VDEC_TAG 0xFE 118 #define MVD_DECODER 1 119 #define HVD_DECODER 2 120 121 122 // _ctl_info task_mode 123 #define CTL_MODE_NORMAL 0 124 #define CTL_MODE_3DWMV 1 // 3d wmv 125 #define CTL_MODE_3DTV 2 // mpeg2+h.264 126 #define CTL_MODE_3DTV_PROG 3 // Korea 3DTV forced progressive mode 127 #define CTL_MODE_ONE_STC 4 // only one STC, sub view sync main stc 128 #define CTL_MODE_SWITCH_STC 5 // switch target STC , main view sync sub stc and sub view sync main stc 129 #define CTL_MODE_3DTV_TWO_PITCH 6 //Korea 3DTV, 2nd pitch enabled for 3DLR 130 #define CTL_MODE_3DTV_PROG_TWO_PITCH 7 // Korea 3DTV PROG, 2nd pitch enabled for 3DLR 131 #define CTL_MODE_SEC_MCU 8 132 133 #define MAX_TASKS 16 // max tasks number 134 #define VSYNC_BRIDGE_TASK_NUM 4 135 136 #define VDEC_FW31 137 138 #ifdef LIGHTWEIGHT //FW31_1.8M 139 #define COMMON_AREA_START 0xB0000 140 #define HEAP_START 0xE0000 141 #else 142 #if defined(SUPPORT_EVD) && (SUPPORT_EVD==1) 143 #define COMMON_AREA_START 0xF0000 144 #define HEAP_START 0x130000 145 #else 146 #define COMMON_AREA_START 0x90000 147 #define HEAP_START 0xC0000 148 #endif 149 #endif 150 151 #define INSIDE_SHM_SIZE 0x200 152 #define INSIDE_SHM_START (COMMON_AREA_START-INSIDE_SHM_SIZE) 153 154 typedef enum 155 { 156 E_CTL_IQMEM_INIT_NONE = 0, 157 E_CTL_IQMEM_INIT_LOADING, //HK -> FW 158 E_CTL_IQMEM_INIT_LOADED, //FW -> HK 159 E_CTL_IQMEM_INIT_FINISH //HK -> FW 160 } CTL_IQMEM_INIT_STATUS; 161 162 typedef enum 163 { 164 E_CTL_DISPLAY_PATH_MVOP_0 = 0, 165 E_CTL_DISPLAY_PATH_MVOP_1, 166 E_CTL_DISPLAY_PATH_MVOP_MAX, 167 E_CTL_DISPLAY_PATH_NONE = 0xff, //display by DIP 168 } CTL_DISPLAY_PATH; 169 170 typedef enum 171 { 172 E_CTL_INPUT_TSP_0 = 0, 173 E_CTL_INPUT_TSP_1 = 1, 174 E_CTL_INPUT_TSP_2 = 2, 175 E_CTL_INPUT_TSP_3 = 3, 176 E_CTL_INPUT_TSP_MAX = 4, 177 E_CTL_INPUT_TSP_NONE = 0xFF, 178 } CTL_INPUT_TSP; 179 180 typedef enum 181 { 182 E_CTL_HDMI_POLICY_NONE = 0, 183 E_CTL_HDMI_POLICY_BLUESCREEN = 1, 184 E_CTL_HDMI_POLICY_SD = 2, 185 E_CTL_HDMI_POLICY_HD = 3, 186 E_CTL_HDMI_POLICY_FHD = 4, 187 E_CTL_HDMI_POLICY_4K = 5, 188 } CTL_HDMI_POLICY; 189 190 191 192 #if 1 193 /* 194 == Common Area Layout == 195 196 +-----------------------------------+ 0x0 197 | HVD_BBU_TBL_SIZE * 4 | 198 +-----------------------------------+ 0x4000 199 | EVD_BBU_TBL_SIZE * 4 | 200 +-----------------------------------+ 0x8000 201 | VP8_BBU_TBL_SIZE * 2 | 202 +-----------------------------------+ 0xA000 203 | MVD_SLQ_TBL_SIZE * 4 | 204 +-----------------------------------+ 0xC000 205 | VSyncBridge structure * 2 | 206 | ds_xc_data_structure (old usage) | 207 +-----------------------------------+ 0xC800 208 | VSyncBridgeExt structure * 2 | 209 +-----------------------------------+ 0xD000 210 | VSyncBridge structure * 2 | 211 +-----------------------------------+ 0xD800 212 | VSyncBridgeExt structure * 2 | 213 +-----------------------------------+ 0xE000 214 | DS IP OP Page | 215 +-----------------------------------+ 0xFF00 216 | DS Scaler Info | 217 +-----------------------------------+ 0x10000 218 219 */ 220 221 #define HVD_BBU_TBL_SIZE 0x1000 222 #define EVD_BBU_TBL_SIZE 0x1000 223 #define VP8_BBU_TBL_SIZE 0x1000 224 #define MVD_SLQ_TBL_SIZE 0x800 225 #define VSYNC_BRIDGE_INFO_SIZE 0x400 226 227 #define HVD_BBU_TBL_OFFSET 0x0 228 #define EVD_BBU_TBL_OFFSET 0x4000 229 #define VP8_BBU_TBL_OFFSET 0x8000 230 #define MVD_SLQ_TBL_OFFSET 0xA000 231 #define VSYNC_BRIDGE_OFFSET 0xC000 // 2 * sizeof(MCU_DISPQ_INFO) + sizeof(ds_xc_data_structure) 232 #define VSYNC_BRIDGE_EXT_OFFSET 0xC800 // 2 * sizeof(MCU_DISPQ_INFO_EXT) 233 #define VSYNC_BRIDGE_NWAY_OFFSET 0xD000 // 2 MCU_DISPQ_INFO, each occupy 0x400 234 #define VSYNC_BRIDGE_EXT_NWAY_OFFSET 0xD800 // 2 MCU_DISPQ_INFO_EXT, each occupy 0x400 235 #define DS_IPOP_PAGE_OFFSET 0xE000 236 #define DS_SCALER_INFO_OFFSET 0xFF00 //0x10F00 237 #else 238 /* 239 == Common Area Layout == 240 241 +-----------------------------------+ 0x0 242 | HVD_BBU_TBL_SIZE * 4 | 243 +-----------------------------------+ 0x4000 244 | EVD_BBU_TBL_SIZE * 4 | 245 +-----------------------------------+ 0x5000 246 | VP8_BBU_TBL_SIZE * 2 | 247 +-----------------------------------+ 0x5800 248 | MVD_SLQ_TBL_SIZE * 4 | 249 +-----------------------------------+ 0x6000 250 | VSyncBridge structure * 2 | 251 | ds_xc_data_structure (old usage) | 252 +-----------------------------------+ 0x6800 253 | VSyncBridgeExt structure * 2 | 254 +-----------------------------------+ 0x7000 255 | VSyncBridge structure * 2 | 256 +-----------------------------------+ 0x7800 257 | VSyncBridgeExt structure * 2 | 258 +-----------------------------------+ 0x8000 259 | DS IP OP Page | 260 +-----------------------------------+ 0x9F00 261 | DS Scaler Info | 262 +-----------------------------------+ 0xA000 263 264 */ 265 266 #define HVD_BBU_TBL_SIZE 0x1000 267 #define EVD_BBU_TBL_SIZE 0x400 268 #define VP8_BBU_TBL_SIZE 0x400 269 #define MVD_SLQ_TBL_SIZE 0x200 270 #define VSYNC_BRIDGE_INFO_SIZE 0x400 271 272 #define HVD_BBU_TBL_OFFSET 0x0 273 #define EVD_BBU_TBL_OFFSET 0x4000 274 #define VP8_BBU_TBL_OFFSET 0x5000 275 #define MVD_SLQ_TBL_OFFSET 0x5800 276 #define VSYNC_BRIDGE_OFFSET 0x6000 277 #define VSYNC_BRIDGE_EXT_OFFSET 0x6800 278 #define VSYNC_BRIDGE_NWAY_OFFSET 0x7000 279 #define VSYNC_BRIDGE_EXT_NWAY_OFFSET 0x7800 280 #define DS_IPOP_PAGE_OFFSET 0x8000 281 #define DS_SCALER_INFO_OFFSET 0x9F00 282 #endif 283 284 #define COMMON_AREA_SIZE 0x10000 285 #define FW_TASK_SIZE 0x100000 286 287 #if defined(SUPPORT_VDEC_STR) 288 /* 289 | STR_FLAG : 16byte | CTL_CMD : 15 set | MAIN_CMD : 120 set | SUB_CMD : 120 set | 290 291 1 set = 16 byte 292 total str buffer ~ 4k 293 */ 294 295 #define VDEC_STR_ALIGN 16 296 #define VDEC_STR_CTL_CMD_RESERVERD 8 297 #define VDEC_STR_CMD_RESERVERD 120 298 299 #if 0 300 #define VDEC_STR_BUFFER_START 0x2B0000 301 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN) 302 #define VDEC_STR_SUB_CTL_CMD_BUF (VDEC_STR_MAIN_CTL_CMD_BUF + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 303 #define VDEC_STR_MAIN_CMD_BUF (VDEC_STR_SUB_CTL_CMD_BUF + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 304 #define VDEC_STR_SUB_CMD_BUF (VDEC_STR_MAIN_CMD_BUF + (VDEC_STR_ALIGN * VDEC_STR_CMD_RESERVERD)) 305 306 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START 307 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1 308 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2 309 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3 310 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4 311 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5 312 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6 313 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE 314 #else 315 316 #define VDEC_STR_BUFFER_DUAL_OFFSET 0x2B0000 317 #define VDEC_STR_BUFFER_SINGLE_OFFSET 0x1D0000 318 319 #define VDEC_STR_MAIN_CTL_CMD_OFFSET (VDEC_STR_ALIGN) 320 #define VDEC_STR_SUB_CTL_CMD_OFFSET (VDEC_STR_MAIN_CTL_CMD_OFFSET + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 321 #define VDEC_STR_MAIN_CMD_OFFSET (VDEC_STR_SUB_CTL_CMD_OFFSET + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 322 #define VDEC_STR_SUB_CMD_OFFSET (VDEC_STR_MAIN_CMD_OFFSET + (VDEC_STR_ALIGN * VDEC_STR_CMD_RESERVERD)) 323 324 #define VDEC_STR_MAIN_WORK_OFFSET 0x0 325 #define VDEC_STR_SUB_WORK_OFFSET 0x1 326 #define VDEC_STR_MAIN_RESUME_OFFSET 0x2 327 #define VDEC_STR_SUB_RESUME_OFFSET 0x3 328 #define VDEC_STR_MAIN_CTL_CMD_COUNT_OFFSET 0x4 329 #define VDEC_STR_SUB_CTL_CMD_COUNT_OFFSET 0x5 330 #define VDEC_STR_MAIN_CMD_COUNT_OFFSET 0x6 331 #define VDEC_STR_SUB_CMD_COUNT_OFFSET 0x8 //0x7 for VDEC_UNMUTE_BYTE 332 333 #endif 334 335 336 337 #define VDEC_STR_CMD 4 338 #define VDEC_STR_ARG0 8 339 #define VDEC_STR_ARG1 9 340 #define VDEC_STR_ARG2 10 341 #define VDEC_STR_ARG3 11 342 #define VDEC_STR_ARG4 12 343 #define VDEC_STR_ARG5 13 344 345 #define VDEC_STR_MVD 1 346 #define VDEC_STR_HVD 2 347 348 #define VDEC_UNMUTE_BYTE 7 349 350 #endif 351 /* Structure definition */ 352 struct _ctl_info { 353 const unsigned int readonly[4]; // CTL_INFO_ADDR + 0x00 read only for tag. 354 unsigned int vpu_clk; // CTL_INFO_ADDR + 0x10 reserved for driver to fw message.(VDEC CPU clock) 355 unsigned int ctl_interface; // CTL_INFO_ADDR + 0x14 driver interface(read only) 356 unsigned int verion; // CTL_INFO_ADDR + 0x18 357 unsigned int statue; // CTL_INFO_ADDR + 0x1C 358 unsigned int last_ctl_cmd; // CTL_INFO_ADDR + 0x20 359 unsigned int last_ctl_arg; // CTL_INFO_ADDR + 0x24 360 unsigned short task_single; // CTL_INFO_ADDR + 0x28 361 unsigned short burst_mode; // CTL_INFO_ADDR + 0x2A 0:normal 1:burst cmd 362 unsigned char task_hvd; // CTL_INFO_ADDR + 0x2C 363 unsigned char task_mvd; // CTL_INFO_ADDR + 0x2D 364 unsigned char task_evd; // CTL_INFO_ADDR + 0x2E 365 unsigned char u8TaskFeature; // CTL_INFO_ADDR + 0x2F 366 367 unsigned char task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment 368 unsigned char task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x40 0:normal 1:3d WMV 2:korea 3d TV 369 unsigned int u32TaskShareInfoAddr[MAX_TASKS]; // CTL_INFO_ADDR + 0x50 offset from FW beginning 370 371 unsigned int u32CommonAreaAddr; // CTL_INFO_ADDR + 0x90 372 373 unsigned int FB_ADDRESS; // CTL_INFO_ADDR + 0x94 , this value is offset of miu, unit is byte 374 unsigned int FB_Total_SIZE; // CTL_INFO_ADDR + 0x98 , unit is byte 375 unsigned int FB_Used_SIZE; // CTL_INFO_ADDR + 0x9C , unit is byte 376 #ifdef VDEC3_FB 377 unsigned int u32FrameBufAddr; // CTL_INFO_ADDR + 0xA0 frame buffer base address 378 unsigned int u32FrameBufSize; // CTL_INFO_ADDR + 0xA4 frame buffer size for all tasks 379 unsigned char u8FrameBufSegment; // CTL_INFO_ADDR + 0xA8 select one enumeration from Split_FB 380 unsigned char bFrameBufUsed[4]; // CTL_INFO_ADDR + 0xA9 record if each segment is used. 381 #endif 382 unsigned char u8UseIMITaskId; // CTL_INFO_ADDR + 0xAD indicate which task is using IMI 383 unsigned char u8HicodecType; // CTL_INFO_ADDR + 0xAE Kano, 0:Hicodec 1:Hicodec_Lite 384 unsigned char u8MultiHVDTaskSameBBU; // CTL_INFO_ADDR + 0xAF 385 unsigned int u32DolbyVisionXCShmAddr; // CTL_INFO_ADDR + 0xB0 record the dolby vision XC share memory address for transfer DM/composer 386 unsigned int u32Reserved; // CTL_INFO_ADDR + 0xB4 387 unsigned char u8STCIndex[MAX_TASKS]; // CTL_INFO_ADDR + 0xB8 388 volatile unsigned char u8IQmemCtrl; // CTL_INFO_ADDR + 0xC8 389 unsigned char bIsIQMEMSupport; // CTL_INFO_ADDR + 0xC9 390 unsigned char bIQmemEnableIfSupport; // CTL_INFO_ADDR + 0xCA 391 unsigned char bReserved; // CTL_INFO_ADDR + 0xCB 392 #if defined(SUPPORT_VDEC_STR) 393 unsigned int u32StrAddrOffset; // CTL_INFO_ADDR + 0xCC 394 #endif 395 } ; 396 397 #define INVALID_ADDR_U32 0xFFFFFFFF 398 399 #ifdef VDEC3 400 #define VDEC_SHARE_MEM_MASK 0x0FFFFFFF 401 #define VDEC_BBU_ID_MASK 0xF0000000 402 #define VDEC_BBU_ID_SHIFT 28 403 404 #define MAX_VDEC_VBBU_ENTRY_COUNT 254 405 406 typedef struct 407 { 408 unsigned int u32Offset; ///< Packet offset from bitstream buffer base address. unit: byte. 409 unsigned int u32Length; ///< Packet size. unit: byte. ==> Move _VDEC_EX_ReparseVP8Packet to FW 410 unsigned long long u64TimeStamp; ///< Packet time stamp. 411 unsigned int u32ID_L; ///< Packet ID low part. 412 unsigned int u32ID_H; ///< Packet ID high part. 413 unsigned char u8Reserved[8]; ///< Revserved space and for 16-byte alignment 414 } VDEC_VBBU_Entry; 415 416 typedef struct 417 { 418 unsigned int u32WrPtr; 419 unsigned int u32RdPtr; 420 unsigned char u8Reserved[8]; 421 VDEC_VBBU_Entry stEntry[MAX_VDEC_VBBU_ENTRY_COUNT + 1]; 422 } VDEC_VBBU; 423 424 #endif 425 426 typedef struct 427 { 428 unsigned int u32HVD_PENDING_RELEASE_ST_ADDR;//[0][0]:0x0D98 [0][1]:0x0DA4 [1][0]:0x0DB0 [1][1]:0x0DBC 429 unsigned int u32HVD_PENDING_RELEASE_SIZE; //[0][0]:0x0D9C [0][1]:0x0DA8 [1][0]:0x0DB4 [1][1]:0x0DC0 430 unsigned int u32HVD_COLLISION_NUM; //[0][0]:0x0DA0 [0][1]:0x0DAC [1][0]:0x0DB8 [1][1]:0x0DC4 431 } PENDING_RELEASE_QUEUE; 432 433 typedef struct 434 { 435 unsigned int u32HVD_DISPCMDQ_DRAM_ST_ADDR;//0x0FA8 // for VDEC3 display command queue usage 436 unsigned int u32HVD_STREAM_DISPCMDQ_RD; //0x0FAC // stream display command queue read ptr for VDEC3 display command queue usage 437 unsigned int u32HVD_STREAM_DISPCMDQ_WD; //0x0FB0 // stream display command queue write ptr for VDEC3 display command queue usage 438 unsigned int u32HVD_CMDQ_DRAM_ST_ADDR; //0x0FB4 // for VDEC3 dram command queue usage 439 unsigned int u32HVD_STREAM_CMDQ_RD; //0x0FB8 // stream command queue read ptr for VDEC3 dram command queue usage 440 unsigned int u32HVD_STREAM_CMDQ_WD; //0x0FBC // stream command queue write ptr for VDEC3 dram command queue usage 441 } CMD_QUEUE; 442 443 typedef struct 444 { 445 unsigned int u32FrameBufAddr; // For main Frame Buffer 446 unsigned int u32FrameBufSize; // For main Frame Buffer 447 unsigned int u32FrameBuf2Addr; // For Balance Frame Buffer 448 unsigned int u32FrameBuf2Size; // For Balance Frame Buffer 449 unsigned char u8FrameBufMiuSel; // For main Frame Buffer 450 unsigned char u8FrameBuf2MiuSel; // For Balance Frame Buffer 451 unsigned short u16Reserved; // Reserved for frame buffer address over 4G 452 } VDEC_INSIDE_FRM_BUF_INFO; 453 454 typedef struct 455 { 456 unsigned char u8code[16];//for magic number 457 unsigned char u8MaxTaskNum; // current==2 458 unsigned char u8Resv[1]; 459 unsigned char u8HDMIPolicyVer; /// HDMI policy version info 460 unsigned char u8HDMIPolicyCnt; /// HDMI policy update count 461 // 32 24 16 8 0 462 // +-----+-----+-----+-----+ 463 // |8bits|8bits|8bits|8bits| 464 // +-----+-----+-----+-----+ 465 // | 4K | FHD | HD | SD | 466 // +-----+-----+-----+-----+ 467 unsigned int u32HDMIPolicyInfo; /// HDMI policy infomation 468 unsigned int u32Resv[31]; 469 VDEC_INSIDE_FRM_BUF_INFO stINSIDE_SHM[2]; 470 } VDEC_INSIDE_SHM; 471 472 extern struct _ctl_info *g_ctl_ptr; 473 extern unsigned char Wakeup_Controller(unsigned char ISR); 474 extern unsigned char CTL_burst_cmd(unsigned int cmd, unsigned int arg); 475 extern volatile char g_ctl_Version[] __attribute__ ((section(".tail_version"), aligned(16))); 476 477 478 #endif // _CONTROL_H_ 479 480