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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _CONTROL_H_ 96 #define _CONTROL_H_ 97 98 extern void CTL_main( void *pvParameters ); 99 extern void CTL_Init(void); 100 extern void CTL_Deinit(void); 101 102 #define CTL_VERSION 0x16083109 103 #define CTL_INFO_ADDR 0x0 104 105 // _ctl_info statue 106 #define CTL_STU_NONE 0 107 #define CTL_STU_INIT 1 108 #define CTL_STU_TASK 2 109 110 // _ctl_info task_statue[x] 111 #define CTL_TASK_NONE 0 112 #define CTL_TASK_CREATE 1 // task has already created by controller 113 #define CTL_TASK_CMDRDY 2 // task has already inited and ready to get command 114 #define CTL_TASK_TO_BE_DELETED 3 // task is going to be deteled 115 #define CTL_TASK_CMD 4 116 117 #define VDEC_TAG 0xFE 118 #define MVD_DECODER 1 119 #define HVD_DECODER 2 120 121 // _ctl_info task_mode 122 #define CTL_MODE_NORMAL 0 123 #define CTL_MODE_3DWMV 1 // 3d wmv 124 #define CTL_MODE_3DTV 2 // mpeg2+h.264 125 #define CTL_MODE_3DTV_PROG 3 // Korea 3DTV forced progressive mode 126 #define CTL_MODE_ONE_STC 4 // only one STC, sub view sync main stc 127 #define CTL_MODE_SWITCH_STC 5 // switch target STC , main view sync sub stc and sub view sync main stc 128 #define CTL_MODE_3DTV_TWO_PITCH 6 //Korea 3DTV, 2nd pitch enabled for 3DLR 129 #define CTL_MODE_3DTV_PROG_TWO_PITCH 7 // Korea 3DTV PROG, 2nd pitch enabled for 3DLR 130 #define CTL_MODE_SEC_MCU 8 131 132 #ifdef VDEC3 133 #define MAX_TASKS 2 // max tasks number 134 #define GLOBAL_NAL_TABLE_BASE_ADDR 0xA4000 135 #define EVD_HVD_BBU_NAL_TABLE_SZIE 0x2000 136 #define NAL_TBL_PRTITION_NUM 2 // This definition should be the same as bbu number 137 #else 138 #define MAX_TASKS 2 // max tasks number 139 #endif 140 141 #define VDEC_FW30 142 143 //fw allocate dram 144 #if defined(SUPPORT_NEW_MEM_LAYOUT) 145 #define DRAM_OFFSET 0x20000 // starts from 0xB0000+0x20000 146 #elif (SUPPORT_EVD) // Local FPGA verification 147 #define DRAM_START 0x100000 148 #else //For HVD and MVD, or real chip verification 149 #define DRAM_START 0xA0000 150 #endif // #if defined(SUPPORT_NEW_MEM_LAYOUT) 151 152 #if defined(SUPPORT_NEW_MEM_LAYOUT) 153 #if defined(SUPPORT_EVD) && (SUPPORT_EVD == 1) 154 #define HEAP_START 0xE0000 155 #else 156 #define HEAP_START 0xC0000 157 #endif 158 #else 159 #define HEAP_START 0xA0000 160 #endif 161 162 #define VSYNC_BRIDGE_OFFSET 0x1FA00 163 #define VSYNC_BRIDGE_EXT_OFFSET 0x20000 164 165 #if defined(SUPPORT_VDEC_STR) 166 /* 167 | STR_FLAG : 16byte | CTL_CMD : 15 set | MAIN_CMD : 120 set | SUB_CMD : 120 set | 168 169 1 set = 16 byte 170 total str buffer ~ 4k 171 */ 172 173 #define VDEC_STR_ALIGN 16 174 #define VDEC_STR_CTL_CMD_RESERVERD 8 175 #define VDEC_STR_CMD_RESERVERD 120 176 177 #if 0 178 #define VDEC_STR_BUFFER_START 0x2B0000 179 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN) 180 #define VDEC_STR_SUB_CTL_CMD_BUF (VDEC_STR_MAIN_CTL_CMD_BUF + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 181 #define VDEC_STR_MAIN_CMD_BUF (VDEC_STR_SUB_CTL_CMD_BUF + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 182 #define VDEC_STR_SUB_CMD_BUF (VDEC_STR_MAIN_CMD_BUF + (VDEC_STR_ALIGN * VDEC_STR_CMD_RESERVERD)) 183 184 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START 185 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1 186 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2 187 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3 188 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4 189 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5 190 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6 191 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE 192 #else 193 194 #define VDEC_STR_BUFFER_DUAL_OFFSET 0x2B0000 195 #define VDEC_STR_BUFFER_SINGLE_OFFSET 0x1D0000 196 197 #define VDEC_STR_MAIN_CTL_CMD_OFFSET (VDEC_STR_ALIGN) 198 #define VDEC_STR_SUB_CTL_CMD_OFFSET (VDEC_STR_MAIN_CTL_CMD_OFFSET + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 199 #define VDEC_STR_MAIN_CMD_OFFSET (VDEC_STR_SUB_CTL_CMD_OFFSET + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 200 #define VDEC_STR_SUB_CMD_OFFSET (VDEC_STR_MAIN_CMD_OFFSET + (VDEC_STR_ALIGN * VDEC_STR_CMD_RESERVERD)) 201 202 #define VDEC_STR_MAIN_WORK_OFFSET 0x0 203 #define VDEC_STR_SUB_WORK_OFFSET 0x1 204 #define VDEC_STR_MAIN_RESUME_OFFSET 0x2 205 #define VDEC_STR_SUB_RESUME_OFFSET 0x3 206 #define VDEC_STR_MAIN_CTL_CMD_COUNT_OFFSET 0x4 207 #define VDEC_STR_SUB_CTL_CMD_COUNT_OFFSET 0x5 208 #define VDEC_STR_MAIN_CMD_COUNT_OFFSET 0x6 209 #define VDEC_STR_SUB_CMD_COUNT_OFFSET 0x8 //0x7 for VDEC_UNMUTE_BYTE 210 211 #endif 212 213 214 215 #define VDEC_STR_CMD 4 216 #define VDEC_STR_ARG0 8 217 #define VDEC_STR_ARG1 9 218 #define VDEC_STR_ARG2 10 219 #define VDEC_STR_ARG3 11 220 #define VDEC_STR_ARG4 12 221 #define VDEC_STR_ARG5 13 222 223 #define VDEC_STR_MVD 1 224 #define VDEC_STR_HVD 2 225 226 #define VDEC_UNMUTE_BYTE 7 227 228 #endif 229 /* Structure defination */ 230 struct _ctl_info { 231 const unsigned int readonly[4]; // CTL_INFO_ADDR + 0x00 read only for tag. 232 unsigned int vpu_clk; // CTL_INFO_ADDR + 0x10 reserved for driver to fw message.(VDEC CPU clock) 233 unsigned int ctl_interface; // CTL_INFO_ADDR + 0x14 driver interface(read only) 234 unsigned int heap_size[MAX_TASKS]; // CTL_INFO_ADDR + 0x18 heap size available for each task 235 unsigned int verion; // CTL_INFO_ADDR + 0x20 236 unsigned int statue; // CTL_INFO_ADDR + 0x24 237 unsigned int last_ctl_cmd; // CTL_INFO_ADDR + 0x28 238 unsigned int last_ctl_arg; // CTL_INFO_ADDR + 0x2C 239 unsigned int task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment 240 unsigned int task_single; // CTL_INFO_ADDR + 0x40 241 unsigned short task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x44 0:normal 1:3d WMV 2:korea 3d TV 242 unsigned int burst_mode; // CTL_INFO_ADDR + 0x48 0:normal 1:burst cmd 243 unsigned char task_hvd; // CTL_INFO_ADDR + 0x4c 244 unsigned char task_mvd; // CTL_INFO_ADDR + 0x4d 245 unsigned short u16TaskFeature; // CTL_INFO_ADDR + 0x4e 246 unsigned int u32Reserved; // CTL_INFO_ADDR + 0x50 reserved 247 unsigned int u32TaskShareInfoAddr[4]; // CTL_INFO_ADDR + 0x54 offset from FW beginning 248 unsigned int u32VsyncBridgeAddr; // CTL_INFO_ADDR + 0x64 249 unsigned int FB_ADDRESS; // CTL_INFO_ADDR + 0x68 , this value is offset of miu, unit is byte 250 unsigned int FB_Total_SIZE; // CTL_INFO_ADDR + 0x6C , unit is byte 251 unsigned int FB_Used_SIZE; // CTL_INFO_ADDR + 0x70 , unit is byte 252 #ifdef VDEC3 253 unsigned int nal_tbl_hvd; 254 unsigned int nal_tbl_evd; 255 unsigned int nal_tbl0_hvd_vp8; 256 unsigned int nal_tbl1_hvd_vp8; 257 #endif 258 #ifdef VDEC3_FB 259 unsigned int u32FrameBufAddr; // frame buffer base address 260 unsigned int u32FrameBufSize; // frame buffer size for all tasks 261 unsigned char u8FrameBufSegment; // select one enumeration from Split_FB 262 unsigned char bFrameBufUsed[4]; // record if each segment is used. 263 #endif 264 unsigned char u8UseIMITaskId; //indicate which task is using IMI 265 unsigned char u8HicodecType; //Kano, 0:Hicodec 1:Hicodec_Lite 266 unsigned char reserved; 267 unsigned int u32VsyncBridgeAddrExt; // record the vsync bridge extension address 268 unsigned int u32DolbyVisionXCShmAddr; // record the dolby vision XC share memory address for transfer DM/composer 269 unsigned char STCindex[MAX_TASKS]; 270 unsigned char STCMode[MAX_TASKS]; 271 unsigned char task_evd; 272 #if defined(SUPPORT_VDEC_STR) 273 unsigned int u32StrAddrOffset; 274 #endif 275 276 } ; 277 278 #ifdef VDEC3 279 #define VDEC_BBU_ID_MASK 0xFF000000 280 #define VDEC_BBU_ID_SHIFT 24 281 282 #define MAX_VDEC_VBBU_ENTRY_COUNT 254 283 284 typedef struct 285 { 286 unsigned int u32Offset; ///< Packet offset from bitstream buffer base address. unit: byte. 287 unsigned int u32Length; ///< Packet size. unit: byte. ==> Move _VDEC_EX_ReparseVP8Packet to FW 288 unsigned long long u64TimeStamp; ///< Packet time stamp. 289 unsigned int u32ID_L; ///< Packet ID low part. 290 unsigned int u32ID_H; ///< Packet ID high part. 291 unsigned char u8Reserved[8]; ///< Revserved space and for 16-byte alignment 292 } VDEC_VBBU_Entry; 293 294 typedef struct 295 { 296 unsigned int u32WrPtr; 297 unsigned int u32RdPtr; 298 unsigned char u8Reserved[8]; 299 VDEC_VBBU_Entry stEntry[MAX_VDEC_VBBU_ENTRY_COUNT + 1]; 300 } VDEC_VBBU; 301 302 #endif 303 304 typedef struct 305 { 306 unsigned int u32HVD_PENDING_RELEASE_ST_ADDR;//[0][0]:0x0D98 [0][1]:0x0DA4 [1][0]:0x0DB0 [1][1]:0x0DBC 307 unsigned int u32HVD_PENDING_RELEASE_SIZE; //[0][0]:0x0D9C [0][1]:0x0DA8 [1][0]:0x0DB4 [1][1]:0x0DC0 308 unsigned int u32HVD_COLLISION_NUM; //[0][0]:0x0DA0 [0][1]:0x0DAC [1][0]:0x0DB8 [1][1]:0x0DC4 309 } PENDING_RELEASE_QUEUE; 310 311 typedef struct 312 { 313 unsigned int u32HVD_DISPCMDQ_DRAM_ST_ADDR;//0x0FA8 // for VDEC3 display command queue usage 314 unsigned int u32HVD_STREAM_DISPCMDQ_RD; //0x0FAC // stream display command queue read ptr for VDEC3 display command queue usage 315 unsigned int u32HVD_STREAM_DISPCMDQ_WD; //0x0FB0 // stream display command queue write ptr for VDEC3 display command queue usage 316 unsigned int u32HVD_CMDQ_DRAM_ST_ADDR; //0x0FB4 // for VDEC3 dram command queue usage 317 unsigned int u32HVD_STREAM_CMDQ_RD; //0x0FB8 // stream command queue read ptr for VDEC3 dram command queue usage 318 unsigned int u32HVD_STREAM_CMDQ_WD; //0x0FBC // stream command queue write ptr for VDEC3 dram command queue usage 319 } CMD_QUEUE; 320 321 extern struct _ctl_info *g_ctl_ptr; 322 extern volatile char g_ctl_Version[] __attribute__ ((section(".tail_version"), aligned(16))); 323 324 325 #endif // _CONTROL_H_ 326 327