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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _CONTROL_H_ 96 #define _CONTROL_H_ 97 98 extern void CTL_main( void *pvParameters ); 99 extern void CTL_Init(void); 100 extern void CTL_Deinit(void); 101 102 #define CTL_VERSION 0x16030821 103 #define CTL_INFO_ADDR 0x0 104 105 // _ctl_info statue 106 #define CTL_STU_NONE 0 107 #define CTL_STU_INIT 1 108 #define CTL_STU_TASK 2 109 110 // _ctl_info task_statue[x] 111 #define CTL_TASK_NONE 0 112 #define CTL_TASK_CREATE 1 // task has already created by controller 113 #define CTL_TASK_CMDRDY 2 // task has already inited and ready to get command 114 #define CTL_TASK_TO_BE_DELETED 3 // task is going to be deteled 115 116 // _ctl_info task_mode 117 #define CTL_MODE_NORMAL 0 118 #define CTL_MODE_3DWMV 1 // 3d wmv 119 #define CTL_MODE_3DTV 2 // mpeg2+h.264 120 #define CTL_MODE_3DTV_PROG 3 // Korea 3DTV forced progressive mode 121 #define CTL_MODE_ONE_STC 4 // only one STC, sub view sync main stc 122 #define CTL_MODE_SWITCH_STC 5 // switch target STC , main view sync sub stc and sub view sync main stc 123 #define CTL_MODE_3DTV_TWO_PITCH 6 //Korea 3DTV, 2nd pitch enabled for 3DLR 124 #define CTL_MODE_3DTV_PROG_TWO_PITCH 7 // Korea 3DTV PROG, 2nd pitch enabled for 3DLR 125 #define CTL_MODE_SEC_MCU 8 126 127 #define MAX_TASKS 16 // max tasks number 128 129 #if defined(SUPPORT_EVD) && (SUPPORT_EVD == 1) 130 #define COMMON_AREA_START 0xF0000 131 #define HEAP_START 0x130000 132 #else 133 #define COMMON_AREA_START 0x90000 134 #define HEAP_START 0xC0000 135 #endif 136 137 /* 138 == Common Buffer Layout == 139 140 +-------------------------------+ 0x0 141 | HVD_BBU_TBL_SIZE * 4 | 142 +-------------------------------+ 0x4000 143 | EVD_BBU_TBL_SIZE * 4 | 144 +-------------------------------+ 0x5000 145 | VP8_BBU_TBL_SIZE * 2 | 146 +-------------------------------+ 0x5800 147 | MVD_SLQ_TBL_SIZE * 4 | 148 +-------------------------------+ 0x6000 149 | VSyncBridge structure * 2 | 150 +-------------------------------+ 0x6800 151 | VSyncBridgeExt structure * 2 | 152 +-------------------------------+ 0x7000 153 | DS IP OP Page | 154 +-------------------------------+ 0x8F00 155 | DS Scaler Info | 156 +-------------------------------+ 0x9000 157 158 */ 159 #if 1 160 #define HVD_BBU_TBL_SIZE 0x1000 161 #define EVD_BBU_TBL_SIZE 0x1000 162 #define VP8_BBU_TBL_SIZE 0x1000 163 #define MVD_SLQ_TBL_SIZE 0x800 164 165 #define HVD_BBU_TBL_OFFSET 0x0 166 #define EVD_BBU_TBL_OFFSET 0x4000 167 #define VP8_BBU_TBL_OFFSET 0x8000 168 #define MVD_SLQ_TBL_OFFSET 0xA000 169 #define VSYNC_BRIDGE_OFFSET 0xC000 170 #define VSYNC_BRIDGE_EXT_OFFSET 0xC800 171 #define DS_IPOP_PAGE_OFFSET 0xE000 172 #define DS_SCALER_INFO_OFFSET 0xFF00 //0x10F00 173 #else 174 #define HVD_BBU_TBL_SIZE 0x1000 175 #define EVD_BBU_TBL_SIZE 0x400 176 #define VP8_BBU_TBL_SIZE 0x400 177 #define MVD_SLQ_TBL_SIZE 0x200 178 179 #define HVD_BBU_TBL_OFFSET 0x0 180 #define EVD_BBU_TBL_OFFSET 0x4000 181 #define VP8_BBU_TBL_OFFSET 0x5000 182 #define MVD_SLQ_TBL_OFFSET 0x5800 183 #define VSYNC_BRIDGE_OFFSET 0x6000 184 #define VSYNC_BRIDGE_EXT_OFFSET 0x6800 185 #define DS_IPOP_PAGE_OFFSET 0x7000 186 #define DS_SCALER_INFO_OFFSET 0x8F00 187 #endif 188 189 #define COMMON_AREA_SIZE 0x10000 190 #define FW_TASK_SIZE 0x100000 191 192 #if defined(SUPPORT_VDEC_STR) 193 /* 194 | STR_FLAG : 16byte | CTL_CMD : 15 set | MAIN_CMD : 120 set | SUB_CMD : 120 set | 195 196 1 set = 16 byte 197 total str buffer ~ 4k 198 */ 199 200 #define VDEC_STR_ALIGN 16 201 #define VDEC_STR_CTL_CMD_RESERVERD 8 202 #define VDEC_STR_CMD_RESERVERD 120 203 204 #if 0 205 #define VDEC_STR_BUFFER_START 0x2B0000 206 #define VDEC_STR_MAIN_CTL_CMD_BUF (VDEC_STR_BUFFER_START + VDEC_STR_ALIGN) 207 #define VDEC_STR_SUB_CTL_CMD_BUF (VDEC_STR_MAIN_CTL_CMD_BUF + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 208 #define VDEC_STR_MAIN_CMD_BUF (VDEC_STR_SUB_CTL_CMD_BUF + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 209 #define VDEC_STR_SUB_CMD_BUF (VDEC_STR_MAIN_CMD_BUF + (VDEC_STR_ALIGN * VDEC_STR_CMD_RESERVERD)) 210 211 #define VDEC_STR_MAIN_WORK VDEC_STR_BUFFER_START 212 #define VDEC_STR_SUB_WORK VDEC_STR_BUFFER_START+0x1 213 #define VDEC_STR_MAIN_RESUME VDEC_STR_BUFFER_START+0x2 214 #define VDEC_STR_SUB_RESUME VDEC_STR_BUFFER_START+0x3 215 #define VDEC_STR_MAIN_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x4 216 #define VDEC_STR_SUB_CTL_CMD_COUNT VDEC_STR_BUFFER_START+0x5 217 #define VDEC_STR_MAIN_CMD_COUNT VDEC_STR_BUFFER_START+0x6 218 #define VDEC_STR_SUB_CMD_COUNT VDEC_STR_BUFFER_START+0x8 //0x7 for VDEC_UNMUTE_BYTE 219 #else 220 221 #define VDEC_STR_BUFFER_DUAL_OFFSET 0x2B0000 222 #define VDEC_STR_BUFFER_SINGLE_OFFSET 0x1D0000 223 224 #define VDEC_STR_MAIN_CTL_CMD_OFFSET (VDEC_STR_ALIGN) 225 #define VDEC_STR_SUB_CTL_CMD_OFFSET (VDEC_STR_MAIN_CTL_CMD_OFFSET + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 226 #define VDEC_STR_MAIN_CMD_OFFSET (VDEC_STR_SUB_CTL_CMD_OFFSET + (VDEC_STR_ALIGN * VDEC_STR_CTL_CMD_RESERVERD)) 227 #define VDEC_STR_SUB_CMD_OFFSET (VDEC_STR_MAIN_CMD_OFFSET + (VDEC_STR_ALIGN * VDEC_STR_CMD_RESERVERD)) 228 229 #define VDEC_STR_MAIN_WORK_OFFSET 0x0 230 #define VDEC_STR_SUB_WORK_OFFSET 0x1 231 #define VDEC_STR_MAIN_RESUME_OFFSET 0x2 232 #define VDEC_STR_SUB_RESUME_OFFSET 0x3 233 #define VDEC_STR_MAIN_CTL_CMD_COUNT_OFFSET 0x4 234 #define VDEC_STR_SUB_CTL_CMD_COUNT_OFFSET 0x5 235 #define VDEC_STR_MAIN_CMD_COUNT_OFFSET 0x6 236 #define VDEC_STR_SUB_CMD_COUNT_OFFSET 0x8 //0x7 for VDEC_UNMUTE_BYTE 237 238 #endif 239 240 241 242 #define VDEC_STR_CMD 4 243 #define VDEC_STR_ARG0 8 244 #define VDEC_STR_ARG1 9 245 #define VDEC_STR_ARG2 10 246 #define VDEC_STR_ARG3 11 247 #define VDEC_STR_ARG4 12 248 #define VDEC_STR_ARG5 13 249 250 #define VDEC_STR_MVD 1 251 #define VDEC_STR_HVD 2 252 253 #define VDEC_UNMUTE_BYTE 7 254 255 #endif 256 /* Structure definition */ 257 struct _ctl_info { 258 const unsigned int readonly[4]; // CTL_INFO_ADDR + 0x00 read only for tag. 259 unsigned int vpu_clk; // CTL_INFO_ADDR + 0x10 reserved for driver to fw message.(VDEC CPU clock) 260 unsigned int ctl_interface; // CTL_INFO_ADDR + 0x14 driver interface(read only) 261 unsigned int verion; // CTL_INFO_ADDR + 0x18 262 unsigned int statue; // CTL_INFO_ADDR + 0x1C 263 unsigned int last_ctl_cmd; // CTL_INFO_ADDR + 0x20 264 unsigned int last_ctl_arg; // CTL_INFO_ADDR + 0x24 265 unsigned short task_single; // CTL_INFO_ADDR + 0x28 266 unsigned short burst_mode; // CTL_INFO_ADDR + 0x2A 0:normal 1:burst cmd 267 unsigned char task_hvd; // CTL_INFO_ADDR + 0x2C 268 unsigned char task_mvd; // CTL_INFO_ADDR + 0x2D 269 unsigned short u16TaskFeature; // CTL_INFO_ADDR + 0x2E 270 271 unsigned char task_statue[MAX_TASKS]; // CTL_INFO_ADDR + 0x30 fixed to 4 elements for alignment 272 unsigned char task_mode[MAX_TASKS]; // CTL_INFO_ADDR + 0x40 0:normal 1:3d WMV 2:korea 3d TV 273 unsigned int u32TaskShareInfoAddr[MAX_TASKS]; // CTL_INFO_ADDR + 0x50 offset from FW beginning 274 275 unsigned int u32HVDBBUTblStAddr; // CTL_INFO_ADDR + 0x90 276 unsigned int u32EVDBBUTblStAddr; // CTL_INFO_ADDR + 0x94 277 unsigned int u32VP8BBUTblStAddr; // CTL_INFO_ADDR + 0x98 278 unsigned int u32MVDSLQTblStAddr; // CTL_INFO_ADDR + 0x9C 279 unsigned int u32VsyncBridgeAddr; // CTL_INFO_ADDR + 0xA0 280 unsigned int u32VsyncBridgeExtAddr; // CTL_INFO_ADDR + 0xA4 281 unsigned int u32DSIPOPAddr; // CTL_INFO_ADDR + 0xA8 282 unsigned int u32DSScalerInfoAddr; // CTL_INFO_ADDR + 0xAC 283 284 unsigned int FB_ADDRESS; // CTL_INFO_ADDR + 0xB0 , this value is offset of miu, unit is byte 285 unsigned int FB_Total_SIZE; // CTL_INFO_ADDR + 0xB4 , unit is byte 286 unsigned int FB_Used_SIZE; // CTL_INFO_ADDR + 0xB8 , unit is byte 287 #ifdef VDEC3_FB 288 unsigned int u32FrameBufAddr; // CTL_INFO_ADDR + 0xBC frame buffer base address 289 unsigned int u32FrameBufSize; // CTL_INFO_ADDR + 0xC0 frame buffer size for all tasks 290 unsigned char u8FrameBufSegment; // CTL_INFO_ADDR + 0xC4 select one enumeration from Split_FB 291 unsigned char bFrameBufUsed[4]; // CTL_INFO_ADDR + 0xC5 record if each segment is used. 292 #endif 293 unsigned char u8UseIMITaskId; // CTL_INFO_ADDR + 0xC9 indicate which task is using IMI 294 unsigned char u8HicodecType; // CTL_INFO_ADDR + 0xCA Kano, 0:Hicodec 1:Hicodec_Lite 295 unsigned char u8MultiHVDTaskSameBBU; // CTL_INFO_ADDR + 0xCB 296 unsigned int u32DolbyVisionXCShmAddr;// CTL_INFO_ADDR + 0xCC record the dolby vision XC share memory address for transfer DM/composer 297 unsigned int u32DVDumpMetaAddrWithXC;// CTL_INFO_ADDR + 0xD0 record dolby meta XC test pattern 298 unsigned char STCindex[2]; // CTL_INFO_ADDR + 0xD4 299 unsigned char STCMode[2]; // CTL_INFO_ADDR + 0xD6 300 #if defined(SUPPORT_VDEC_STR) 301 unsigned int u32StrAddrOffset; // CTL_INFO_ADDR + 0xD8 302 #endif 303 } ; 304 305 #define INVALID_ADDR_U32 0xFFFFFFFF 306 307 #ifdef VDEC3 308 #define VDEC_SHARE_MEM_MASK 0x0FFFFFFF 309 #define VDEC_BBU_ID_MASK 0xF0000000 310 #define VDEC_BBU_ID_SHIFT 28 311 312 #define MAX_VDEC_VBBU_ENTRY_COUNT 254 313 314 typedef struct 315 { 316 unsigned int u32Offset; ///< Packet offset from bitstream buffer base address. unit: byte. 317 unsigned int u32Length; ///< Packet size. unit: byte. ==> Move _VDEC_EX_ReparseVP8Packet to FW 318 unsigned long long u64TimeStamp; ///< Packet time stamp. 319 unsigned int u32ID_L; ///< Packet ID low part. 320 unsigned int u32ID_H; ///< Packet ID high part. 321 unsigned char u8Reserved[8]; ///< Revserved space and for 16-byte alignment 322 } VDEC_VBBU_Entry; 323 324 typedef struct 325 { 326 unsigned int u32WrPtr; 327 unsigned int u32RdPtr; 328 unsigned char u8Reserved[8]; 329 VDEC_VBBU_Entry stEntry[MAX_VDEC_VBBU_ENTRY_COUNT + 1]; 330 } VDEC_VBBU; 331 332 #endif 333 334 typedef struct 335 { 336 unsigned int u32HVD_PENDING_RELEASE_ST_ADDR;//[0][0]:0x0D98 [0][1]:0x0DA4 [1][0]:0x0DB0 [1][1]:0x0DBC 337 unsigned int u32HVD_PENDING_RELEASE_SIZE; //[0][0]:0x0D9C [0][1]:0x0DA8 [1][0]:0x0DB4 [1][1]:0x0DC0 338 unsigned int u32HVD_COLLISION_NUM; //[0][0]:0x0DA0 [0][1]:0x0DAC [1][0]:0x0DB8 [1][1]:0x0DC4 339 } PENDING_RELEASE_QUEUE; 340 341 typedef struct 342 { 343 unsigned int u32HVD_DISPCMDQ_DRAM_ST_ADDR;//0x0FA8 // for VDEC3 display command queue usage 344 unsigned int u32HVD_STREAM_DISPCMDQ_RD; //0x0FAC // stream display command queue read ptr for VDEC3 display command queue usage 345 unsigned int u32HVD_STREAM_DISPCMDQ_WD; //0x0FB0 // stream display command queue write ptr for VDEC3 display command queue usage 346 unsigned int u32HVD_CMDQ_DRAM_ST_ADDR; //0x0FB4 // for VDEC3 dram command queue usage 347 unsigned int u32HVD_STREAM_CMDQ_RD; //0x0FB8 // stream command queue read ptr for VDEC3 dram command queue usage 348 unsigned int u32HVD_STREAM_CMDQ_WD; //0x0FBC // stream command queue write ptr for VDEC3 dram command queue usage 349 } CMD_QUEUE; 350 351 extern struct _ctl_info *g_ctl_ptr; 352 extern unsigned char Wakeup_Controller(unsigned char ISR); 353 extern unsigned char CTL_burst_cmd(unsigned int cmd, unsigned int arg); 354 extern volatile char g_ctl_Version[] __attribute__ ((section(".tail_version"), aligned(16))); 355 356 357 #endif // _CONTROL_H_ 358 359