| /utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/ |
| H A D | halAVD.c | 172 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
6330 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6331 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6336 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6339 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6342 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6345 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6348 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6351 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6354 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
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| /utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/ |
| H A D | halAVD.c | 172 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
6330 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6331 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6336 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6339 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6342 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6345 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6348 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6351 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6354 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
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| /utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/ |
| H A D | halAVD.c | 172 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
6330 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6331 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6336 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6339 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6342 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6345 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6348 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6351 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6354 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
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| /utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/ |
| H A D | halAVD.c | 172 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
6330 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6331 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6336 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6339 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6342 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6345 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6348 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6351 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6354 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
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| /utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/ |
| H A D | halAVD.c | 172 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
6330 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6331 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6336 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6339 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6342 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6345 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6348 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6351 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6354 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
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| /utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/ |
| H A D | halAVD.c | 166 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
6315 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6316 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6321 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6324 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6327 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6330 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6333 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6336 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6339 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
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| /utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/ |
| H A D | halAVD.c | 171 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
6329 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6330 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6335 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6338 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6341 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6344 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6347 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6350 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6353 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
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| /utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/ |
| H A D | halAVD.c | 166 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
6315 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6316 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6321 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6324 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6327 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6330 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6333 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6336 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6339 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
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| /utopia/UTPA2-700.0.x/modules/vd/hal/macan/avd/ |
| H A D | halAVD.c | 166 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
6317 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6318 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6323 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6326 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6329 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6332 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6335 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6338 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6341 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
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| /utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/ |
| H A D | halAVD.c | 167 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
2971 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
2972 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
2977 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2980 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2983 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2986 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2989 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2992 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2995 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
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| /utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/ |
| H A D | halAVD.c | 167 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
2971 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
2972 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
2977 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2980 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2983 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2986 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2989 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2992 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2995 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
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| /utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/ |
| H A D | halAVD.c | 166 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
2970 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
2971 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
2976 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2979 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2982 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2985 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2988 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2991 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2994 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
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| /utopia/UTPA2-700.0.x/modules/vif/hal/maldives/vif/ |
| H A D | halVIF.c | 186 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
1347 RIU_WriteByteMask(u32Reg, u8Val, u8Mask); in msWriteByteMask()
1447 … RIU_WriteByteMask(0x1E39L, 0x00, 0x03); // DMDTOP/DMDANA_controlled by HK_MCU (0) or DMD_MCU (1) in msVifAdcInitial()
1480 RIU_WriteByteMask(0x12879L, 0x00, 0xF0); // Enable LDOs in msVifAdcInitial()
1514 RIU_WriteByteMask(RFAGC_DATA_SEL, 0, 0x0C); // RFAGC in msVifAdcInitial()
1515 RIU_WriteByteMask(IFAGC_DATA_SEL, 0, 0xC0); // IFAGC in msVifAdcInitial()
3695 RIU_WriteByteMask(0x120A2L, 0x01, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
3696 RIU_WriteByteMask(0x120A2L, 0x03, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
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| /utopia/UTPA2-700.0.x/modules/vif/hal/manhattan/vif/ |
| H A D | halVIF.c | 186 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
1337 RIU_WriteByteMask(u32Reg, u8Val, u8Mask); in msWriteByteMask()
1437 … RIU_WriteByteMask(0x1E39L, 0x00, 0x03); // DMDTOP/DMDANA_controlled by HK_MCU (0) or DMD_MCU (1) in msVifAdcInitial()
1483 RIU_WriteByteMask(0x12879L, 0x00, 0xF0); // Enable LDOS in msVifAdcInitial()
1527 RIU_WriteByteMask(RFAGC_DATA_SEL, 0, 0x0C); // RFAGC in msVifAdcInitial()
1528 RIU_WriteByteMask(IFAGC_DATA_SEL, 0, 0xC0); // IFAGC in msVifAdcInitial()
3703 RIU_WriteByteMask(0x120A2L, 0x01, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
3704 RIU_WriteByteMask(0x120A2L, 0x03, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
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| /utopia/UTPA2-700.0.x/modules/vif/hal/mainz/vif/ |
| H A D | halVIF.c | 186 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
1333 RIU_WriteByteMask(u32Reg, u8Val, u8Mask); in msWriteByteMask()
1433 … RIU_WriteByteMask(0x1E39L, 0x00, 0x03); // DMDTOP/DMDANA_controlled by HK_MCU (0) or DMD_MCU (1) in msVifAdcInitial()
1481 RIU_WriteByteMask(0x12879L, 0x00, 0xF0); // Enable LDOS in msVifAdcInitial()
1525 RIU_WriteByteMask(RFAGC_DATA_SEL, 0, 0x0C); // RFAGC in msVifAdcInitial()
1526 RIU_WriteByteMask(IFAGC_DATA_SEL, 0, 0xC0); // IFAGC in msVifAdcInitial()
3691 RIU_WriteByteMask(0x120A2L, 0x01, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
3692 RIU_WriteByteMask(0x120A2L, 0x03, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
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| /utopia/UTPA2-700.0.x/modules/vif/hal/messi/vif/ |
| H A D | halVIF.c | 186 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
1333 RIU_WriteByteMask(u32Reg, u8Val, u8Mask); in msWriteByteMask()
1433 … RIU_WriteByteMask(0x1E39L, 0x00, 0x03); // DMDTOP/DMDANA_controlled by HK_MCU (0) or DMD_MCU (1) in msVifAdcInitial()
1481 RIU_WriteByteMask(0x12879L, 0x00, 0xF0); // Enable LDOS in msVifAdcInitial()
1525 RIU_WriteByteMask(RFAGC_DATA_SEL, 0, 0x0C); // RFAGC in msVifAdcInitial()
1526 RIU_WriteByteMask(IFAGC_DATA_SEL, 0, 0xC0); // IFAGC in msVifAdcInitial()
3691 RIU_WriteByteMask(0x120A2L, 0x01, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
3692 RIU_WriteByteMask(0x120A2L, 0x03, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
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| /utopia/UTPA2-700.0.x/modules/vif/hal/mustang/vif/ |
| H A D | halVIF.c | 186 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
1355 RIU_WriteByteMask(u32Reg, u8Val, u8Mask); in msWriteByteMask()
1455 … RIU_WriteByteMask(0x1E39L, 0x00, 0x03); // DMDTOP/DMDANA_controlled by HK_MCU (0) or DMD_MCU (1) in msVifAdcInitial()
1610 RIU_WriteByteMask(RFAGC_DATA_SEL, 0, 0x0C); // RFAGC in msVifAdcInitial()
1611 RIU_WriteByteMask(IFAGC_DATA_SEL, 0, 0xC0); // IFAGC in msVifAdcInitial()
3823 RIU_WriteByteMask(0x120A2L, 0x01, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
3824 RIU_WriteByteMask(0x120A2L, 0x03, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
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| /utopia/UTPA2-700.0.x/modules/vif/hal/mooney/vif/ |
| H A D | halVIF.c | 186 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
1356 RIU_WriteByteMask(u32Reg, u8Val, u8Mask); in msWriteByteMask()
1456 … RIU_WriteByteMask(0x1E39L, 0x00, 0x03); // DMDTOP/DMDANA_controlled by HK_MCU (0) or DMD_MCU (1) in msVifAdcInitial()
1623 RIU_WriteByteMask(RFAGC_DATA_SEL, 0, 0x0C); // RFAGC in msVifAdcInitial()
1624 RIU_WriteByteMask(IFAGC_DATA_SEL, 0, 0xC0); // IFAGC in msVifAdcInitial()
3851 RIU_WriteByteMask(0x120A2L, 0x01, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
3852 RIU_WriteByteMask(0x120A2L, 0x03, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
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| /utopia/UTPA2-700.0.x/modules/vif/hal/maserati/vif/ |
| H A D | halVIF.c | 186 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
1546 RIU_WriteByteMask(u32Reg, u8Val, u8Mask); in msWriteByteMask()
1646 … RIU_WriteByteMask(0x1E39L, 0x00, 0x03); // DMDTOP/DMDANA_controlled by HK_MCU (0) or DMD_MCU (1) in msVifAdcInitial()
1801 RIU_WriteByteMask(RFAGC_DATA_SEL, 0, 0x0C); // RFAGC in msVifAdcInitial()
1802 RIU_WriteByteMask(IFAGC_DATA_SEL, 0, 0xC0); // IFAGC in msVifAdcInitial()
4032 RIU_WriteByteMask(0x120A2L, 0x01, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
4033 RIU_WriteByteMask(0x120A2L, 0x03, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
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| /utopia/UTPA2-700.0.x/modules/vif/hal/M7821/vif/ |
| H A D | halVIF.c | 186 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
1546 RIU_WriteByteMask(u32Reg, u8Val, u8Mask); in msWriteByteMask()
1646 … RIU_WriteByteMask(0x1E39L, 0x00, 0x03); // DMDTOP/DMDANA_controlled by HK_MCU (0) or DMD_MCU (1) in msVifAdcInitial()
1801 RIU_WriteByteMask(RFAGC_DATA_SEL, 0, 0x0C); // RFAGC in msVifAdcInitial()
1802 RIU_WriteByteMask(IFAGC_DATA_SEL, 0, 0xC0); // IFAGC in msVifAdcInitial()
4032 RIU_WriteByteMask(0x120A2L, 0x01, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
4033 RIU_WriteByteMask(0x120A2L, 0x03, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
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| /utopia/UTPA2-700.0.x/modules/vif/hal/maxim/vif/ |
| H A D | halVIF.c | 186 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
1546 RIU_WriteByteMask(u32Reg, u8Val, u8Mask); in msWriteByteMask()
1646 … RIU_WriteByteMask(0x1E39L, 0x00, 0x03); // DMDTOP/DMDANA_controlled by HK_MCU (0) or DMD_MCU (1) in msVifAdcInitial()
1811 RIU_WriteByteMask(RFAGC_DATA_SEL, 0, 0x0C); // RFAGC in msVifAdcInitial()
1812 RIU_WriteByteMask(IFAGC_DATA_SEL, 0, 0xC0); // IFAGC in msVifAdcInitial()
4050 RIU_WriteByteMask(0x120A2L, 0x01, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
4051 RIU_WriteByteMask(0x120A2L, 0x03, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
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| /utopia/UTPA2-700.0.x/modules/vif/hal/M7621/vif/ |
| H A D | halVIF.c | 186 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
1546 RIU_WriteByteMask(u32Reg, u8Val, u8Mask); in msWriteByteMask()
1646 … RIU_WriteByteMask(0x1E39L, 0x00, 0x03); // DMDTOP/DMDANA_controlled by HK_MCU (0) or DMD_MCU (1) in msVifAdcInitial()
1802 RIU_WriteByteMask(RFAGC_DATA_SEL, 0, 0x0C); // RFAGC in msVifAdcInitial()
1803 RIU_WriteByteMask(IFAGC_DATA_SEL, 0, 0xC0); // IFAGC in msVifAdcInitial()
4041 RIU_WriteByteMask(0x120A2L, 0x01, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
4042 RIU_WriteByteMask(0x120A2L, 0x03, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
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| /utopia/UTPA2-700.0.x/modules/vif/hal/macan/vif/ |
| H A D | halVIF.c | 186 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
1542 RIU_WriteByteMask(u32Reg, u8Val, u8Mask); in msWriteByteMask()
1642 … RIU_WriteByteMask(0x1E39L, 0x00, 0x03); // DMDTOP/DMDANA_controlled by HK_MCU (0) or DMD_MCU (1) in msVifAdcInitial()
1797 RIU_WriteByteMask(RFAGC_DATA_SEL, 0, 0x0C); // RFAGC in msVifAdcInitial()
1798 RIU_WriteByteMask(IFAGC_DATA_SEL, 0, 0xC0); // IFAGC in msVifAdcInitial()
4015 RIU_WriteByteMask(0x120A2L, 0x01, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
4016 RIU_WriteByteMask(0x120A2L, 0x03, 0x0F); // reg_vif_fir_coef_ctrl in msVifLoadEQCoeff()
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| /utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/ |
| H A D | halDMD_INTERN_common.c | 161 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
402 RIU_WriteByteMask(u32Addr, u8Value, u8Mask); in HAL_DMD_RIU_WriteByteMask()
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| /utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/ |
| H A D | halDMD_INTERN_common.c | 161 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
402 RIU_WriteByteMask(u32Addr, u8Value, u8Mask); in HAL_DMD_RIU_WriteByteMask()
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