Lines Matching refs:RIU_WriteByteMask
172 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ macro
6330 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6331 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6336 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6339 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6342 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6345 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6348 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6351 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6354 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6357 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6360 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6366 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BIT(1)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6370 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(1), BIT(1)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6394 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6395 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6400 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6403 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6406 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6409 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6412 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6415 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6418 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6421 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6424 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6430 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BIT(1)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6434 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(1), BIT(1)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6520 RIU_WriteByteMask(VD_MCU_KEY, 0x50, 0xF0); in HAL_AVD_VDMCU_LoadDSP()
6559 RIU_WriteByteMask(VD_MCU_KEY, 0x00, 0xF0); in HAL_AVD_VDMCU_LoadDSP()
6858 RIU_WriteByteMask (BK_AFEC_D4, u8AfecD4, BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
6859 RIU_WriteByteMask (BK_AFEC_D5, u8AfecD5, BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
6860 RIU_WriteByteMask (BK_AFEC_D8, u8AfecD8 & (~ BIT(3)), BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
6861 RIU_WriteByteMask (BK_AFEC_D9, u8AfecD9, BMASK(7:4)); in HAL_AVD_AFEC_McuReset()
6886 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6887 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6888 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6889 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6900 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0xFF, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6901 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0xFF, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6902 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0xFF, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6903 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0xFF, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6947 …RIU_WriteByteMask(H_BK_CLKGEN0(0x21), 0x00<<2, BMASK(3:2)); // 20090628 BY put VD200 clock settin… in HAL_AVD_AFEC_SetClock()
6948 RIU_WriteByteMask (L_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox0 in HAL_AVD_AFEC_SetClock()
6949 RIU_WriteByteMask (H_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox1 in HAL_AVD_AFEC_SetClock()
6989 RIU_WriteByteMask(L_BK_ADC_ATOP(0x04), 0x00, (BIT(3)|BIT(2)|BIT(1)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6990 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(3))); in HAL_AVD_AFEC_SetClockSource()
6991 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClockSource()
6992 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6993 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4)|BIT(2))); in HAL_AVD_AFEC_SetClockSource()
6994 RIU_WriteByteMask(H_BK_ADC_ATOP(0x5E), 0x00, (BIT(5))); // new after T4 in HAL_AVD_AFEC_SetClockSource()
7153 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7173 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7195 RIU_WriteByteMask(BK_AFEC_A2, 0x20,(BIT(4)|BIT(5))); // Disable 2-line-delay in HAL_AVD_AFEC_SetInput()
7233 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7325 RIU_WriteByteMask( u16Temp + u8Adr, u8Value, u8Mask ); in HAL_AVD_AFEC_SetRegFromDSP()
7326 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7343 RIU_WriteByteMask( BK_AFEC_DF, u8Value, 0xFF ); in HAL_AVD_AFEC_SetRegFromDSP()
7344 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
7410 RIU_WriteByteMask( BK_AFEC_CF, u8Mode << 0, BMASK(1:0) ); in HAL_AVD_AFEC_SetVtotal()
7479 RIU_WriteByteMask( BK_AFEC_CE, (u8FSCMode) << 1, BMASK(3:1) ); in HAL_AVD_AFEC_SetFSCMode()
7532 RIU_WriteByteMask(BK_AFEC_39, 0x03, BIT(1) | BIT(0)); // more reliability in HAL_AVD_AFEC_EnableBottomAverage()
7536 RIU_WriteByteMask(BK_AFEC_39, 0x00, BIT(1) | BIT(0)); // more sensitivity in HAL_AVD_AFEC_EnableBottomAverage()
7572 RIU_WriteByteMask (BK_AFEC_43, u8AgcMode << 5, BMASK(6:5)); in HAL_AVD_AFEC_AGCSetMode()
7593 RIU_WriteByteMask (BK_AFEC_3F, u8AgcCoarseGain, BMASK(3:0) ); in HAL_AVD_AFEC_AGCSetCoarseGain()
7656 RIU_WriteByteMask (BK_AFEC_9A, eVDHsyncSensitivityTuning.u8CNTRFailBeforeLock<< 4, BMASK(7:4)); in HAL_AVD_AFEC_SetHsyncSensitivity()
7657 RIU_WriteByteMask (BK_AFEC_9B, eVDHsyncSensitivityTuning.u8CNTRSyncBeforeLock << 0, BMASK(5:0)); in HAL_AVD_AFEC_SetHsyncSensitivity()
7658 RIU_WriteByteMask (BK_AFEC_9C, eVDHsyncSensitivityTuning.u8CNTRSyncAfterLock << 0, BMASK(5:0)); in HAL_AVD_AFEC_SetHsyncSensitivity()
7675 RIU_WriteByteMask (BK_AFEC_D8, u8Limit<< 4, BMASK(7:4)); in HAL_AVD_AFEC_SetSwingLimit()
7692 RIU_WriteByteMask( BK_AFEC_D8, BIT(3), BIT(3) ); // auto clear to 0 by dsp in HAL_AVD_AFEC_SetChannelChange()
7818 RIU_WriteByteMask( BK_COMB_10, 0x07, 0x07 ); in HAL_AVD_COMB_Set3dComb()
7833 RIU_WriteByteMask( BK_COMB_10, 0x02, 0x07 ); // 0x12 is recommended by designer in HAL_AVD_COMB_Set3dComb()
7854 RIU_WriteByteMask(BK_COMB_5F, u8COMB5F, BMASK(7:4)); in HAL_AVD_COMB_Set3dCombSpeed()
7890 RIU_WriteByteMask(BK_COMB_23, 0x02, BIT(3) | BIT(1)); in HAL_AVD_COMB_Set3dFineTune()
7896 RIU_WriteByteMask(BK_COMB_23, 0x08, BIT(3) | BIT(1)); in HAL_AVD_COMB_Set3dFineTune()
7977 RIU_WriteByteMask( BK_COMB_48, u8YCPipe, 0x30 ); in HAL_AVD_COMB_SetYCPipe()
7994 RIU_WriteByteMask( BK_COMB_6C, u8CbCrInverse, 0x0C ); in HAL_AVD_COMB_SetCbCrInverse()
8011 RIU_WriteByteMask( BK_COMB_40, u8Mode, (BIT(1)|BIT(0))); in HAL_AVD_COMB_SetVerticalTimingDetectMode()
8028 RIU_WriteByteMask(BK_COMB_50, u8Mode, 0x07); in HAL_AVD_COMB_SetLineBufferMode()
8127 RIU_WriteByteMask(BK_COMB_FF, 0x00, (BIT(1))); in HAL_AVD_COMB_SetMemoryRequest()
8136 RIU_WriteByteMask(BK_COMB_2A, 0x00, (BIT(4))); //weicheng 20130124 COMB memory issue. in HAL_AVD_COMB_SetMemoryRequest()
8147 RIU_WriteByteMask(BK_COMB_2A, 0x10, (BIT(4))); //weicheng 20121008 COMB memory issue. in HAL_AVD_COMB_SetMemoryRequest()
8151 RIU_WriteByteMask(BK_COMB_FF, 0x02, (BIT(1))); in HAL_AVD_COMB_SetMemoryRequest()
8483 RIU_WriteByteMask(BK_AFEC_4C, u8BusrtStartPosition, 0x1F); in HAL_AVD_SetBurstWinStart()