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Searched refs:REG_MOD_BK00_64_L (Results 1 – 11 of 11) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A DhalPNL.c2955 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_OC_Handshake()
2956 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_OC_Handshake()
2957 … MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_OC_Handshake()
2958 …MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_OC_Handshake()
2959 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_OC_Handshake()
2975 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
2993 if(MOD_R2BYTEMSK(REG_MOD_BK00_64_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_OC_Handshake()
2995 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
3170 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd000); in MHal_PNL_SetOSDCOutputType()
3171 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd330); in MHal_PNL_SetOSDCOutputType()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A DhalPNL.c3353 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_OC_Handshake()
3354 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_OC_Handshake()
3355 … MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_OC_Handshake()
3356 …MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_OC_Handshake()
3357 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_OC_Handshake()
3373 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
3391 if(MOD_R2BYTEMSK(REG_MOD_BK00_64_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_OC_Handshake()
3393 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
3568 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd000); in MHal_PNL_SetOSDCOutputType()
3569 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd330); in MHal_PNL_SetOSDCOutputType()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A DhalPNL.c3654 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_OC_Handshake()
3655 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_OC_Handshake()
3656 … MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_OC_Handshake()
3657 …MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_OC_Handshake()
3658 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_OC_Handshake()
3674 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
3692 if(MOD_R2BYTEMSK(REG_MOD_BK00_64_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_OC_Handshake()
3694 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
3880 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd000); in MHal_PNL_SetOSDCOutputType()
3881 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd330); in MHal_PNL_SetOSDCOutputType()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A DhalPNL.c2625 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_OC_Handshake()
2626 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_OC_Handshake()
2627 … MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_OC_Handshake()
2628 …MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_OC_Handshake()
2629 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_OC_Handshake()
2645 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
2663 if(MOD_R2BYTEMSK(REG_MOD_BK00_64_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_OC_Handshake()
2665 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
3006 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0AAE); in MHal_PNL_VBY1_Hardware_TrainingMode_En()
3010 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0AA6); in MHal_PNL_VBY1_Hardware_TrainingMode_En()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A DhalPNL.c2625 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_OC_Handshake()
2626 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_OC_Handshake()
2627 … MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_OC_Handshake()
2628 …MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_OC_Handshake()
2629 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_OC_Handshake()
2645 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
2663 if(MOD_R2BYTEMSK(REG_MOD_BK00_64_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_OC_Handshake()
2665 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
3006 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0AAE); in MHal_PNL_VBY1_Hardware_TrainingMode_En()
3010 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0AA6); in MHal_PNL_VBY1_Hardware_TrainingMode_En()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.c3700 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_OC_Handshake()
3701 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_OC_Handshake()
3702 … MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_OC_Handshake()
3703 …MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_OC_Handshake()
3704 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_OC_Handshake()
3720 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
3738 if(MOD_R2BYTEMSK(REG_MOD_BK00_64_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_OC_Handshake()
3740 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
3926 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd000); in MHal_PNL_SetOSDCOutputType()
3927 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd330); in MHal_PNL_SetOSDCOutputType()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A DhalPNL.c3700 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_OC_Handshake()
3701 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_OC_Handshake()
3702 … MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_OC_Handshake()
3703 …MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_OC_Handshake()
3704 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_OC_Handshake()
3720 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
3738 if(MOD_R2BYTEMSK(REG_MOD_BK00_64_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_OC_Handshake()
3740 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
3926 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd000); in MHal_PNL_SetOSDCOutputType()
3927 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd330); in MHal_PNL_SetOSDCOutputType()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A DhalPNL.c3365 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x003F, 0x003F); in MHal_PNL_SetOutputType()
4611 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_OC_Handshake()
4612 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_OC_Handshake()
4613 … MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_OC_Handshake()
4614 …MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_OC_Handshake()
4615 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_OC_Handshake()
4631 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
4649 if(MOD_R2BYTEMSK(REG_MOD_BK00_64_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_OC_Handshake()
4651 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
4910 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x0000, BIT(10)); in MHal_PNL_SetOSDCOutputType()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A DhalPNL.c3392 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x003F, 0x003F); in MHal_PNL_SetOutputType()
4638 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_OC_Handshake()
4639 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_OC_Handshake()
4640 … MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_OC_Handshake()
4641 …MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_OC_Handshake()
4642 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_OC_Handshake()
4658 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
4676 if(MOD_R2BYTEMSK(REG_MOD_BK00_64_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_OC_Handshake()
4678 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE); in MHal_PNL_VBY1_OC_Handshake()
4940 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x0000, BIT(10)); in MHal_PNL_SetOSDCOutputType()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/
H A Dhwreg_mod.h309 #define REG_MOD_BK00_64_L _PK_L_(0x00, 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/drv/pnl/include/
H A Dpnl_hwreg_utility2.h1900 #define REG_MOD_BK00_64_L _PK_L_(0x00, 0x64) macro