Searched refs:REG_CLKGEN0_TS_INVERT (Results 1 – 14 of 14) sorted by relevance
931 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()934 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()937 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()940 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()943 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS4_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS4_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()946 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS5_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()949 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS6_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS6_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()960 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()963 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()966 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()[all …]
108 #define REG_CLKGEN0_TS_INVERT 0x0002 macro
866 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()869 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()872 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()883 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()886 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()889 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()5013 …_REG(REG_CLKGEN0_TS0_CLK) >> REG_CLKGEN0_TS0_SHIFT)& REG_CLKGEN0_TS_INVERT) == REG_CLKGEN0_TS_INVE… in HAL_TSP_GetTSIF_Status()5024 …_REG(REG_CLKGEN0_TS1_CLK) >> REG_CLKGEN0_TS1_SHIFT)& REG_CLKGEN0_TS_INVERT) == REG_CLKGEN0_TS_INVE… in HAL_TSP_GetTSIF_Status()5035 …_REG(REG_CLKGEN0_TS2_CLK) >> REG_CLKGEN0_TS2_SHIFT)& REG_CLKGEN0_TS_INVERT) == REG_CLKGEN0_TS_INVE… in HAL_TSP_GetTSIF_Status()
96 #define REG_CLKGEN0_TS_INVERT 0x0002 macro
1440 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1443 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1446 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1449 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1460 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1463 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1466 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1469 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()
107 #define REG_CLKGEN0_TS_INVERT 0x0002 macro
1374 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1377 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1380 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1383 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1394 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1397 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1400 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1403 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()
103 #define REG_CLKGEN0_TS_INVERT 0x0002 macro
1471 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1474 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1477 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1480 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1491 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1494 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1497 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1500 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()