Searched refs:REG_CLKGEN0_TSO0_SHIFT (Results 1 – 14 of 14) sorted by relevance
89 #define REG_CLKGEN0_TSO0_SHIFT 0 macro
628 … = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TSO0_SHIFT)); in HAL_TSP_Power()
85 #define REG_CLKGEN0_TSO0_SHIFT 0 macro
850 | (u32CLKSrc << (REG_CLKGEN0_TSO0_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT)); in HAL_TSP_TSO_TSIF_SelPad()
96 #define REG_CLKGEN0_TSO0_SHIFT 0 macro
712 … = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TSO0_SHIFT)); in HAL_TSP_Power()1423 | (u32CLKSrc << (REG_CLKGEN0_TSO0_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT)); in HAL_TSP_TSO_TSIF_SelPad()
92 #define REG_CLKGEN0_TSO0_SHIFT 0 macro
735 … = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TSO0_SHIFT)); in HAL_TSP_Power()1454 | (u32CLKSrc << (REG_CLKGEN0_TSO0_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT)); in HAL_TSP_TSO_TSIF_SelPad()
636 … = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TSO0_SHIFT)); in HAL_TSP_Power()1357 | (u32CLKSrc << (REG_CLKGEN0_TSO0_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT)); in HAL_TSP_TSO_TSIF_SelPad()