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Searched refs:REG_CLKGEN0_TS3_SHIFT (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DhalTSP.c528 …S3_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_Power()
622 … = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_Power()
893 …(REG_CLKGEN0_TS3_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS3_SHIFT)) | (clk_src<<(REG_CLKGEN0_TS… in HAL_TSP_TSIF_SelPad()
940 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()
969 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()
1022 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkDis()
1068 …N0_REG(REG_CLKGEN0_TS3_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS3_SHIFT)) >> (REG_CLKGEN0_TS3_SH… in HAL_TSP_TSIF_SelPad_ClkDis()
1105 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkDis()
H A DregTSP.h98 #define REG_CLKGEN0_TS3_SHIFT 8 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DhalTSP.c622 …S3_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_Power()
709 … = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_Power()
1130 …_TS3_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS3_SHIFT)) in HAL_TSP_TSIF_SelPad()
1131 … | (clk_src<<(REG_CLKGEN0_TS3_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT)); in HAL_TSP_TSIF_SelPad()
1449 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()
1469 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()
1519 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkDis()
1560 …N0_REG(REG_CLKGEN0_TS3_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS3_SHIFT)) >> (REG_CLKGEN0_TS3_SH… in HAL_TSP_TSIF_SelPad_ClkDis()
1612 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkDis()
H A DregTSP.h104 #define REG_CLKGEN0_TS3_SHIFT 8 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DhalTSP.c546 …S3_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_Power()
633 … = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_Power()
1068 …(REG_CLKGEN0_TS3_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS3_SHIFT)) | (clk_src<<(REG_CLKGEN0_TS… in HAL_TSP_TSIF_SelPad()
1383 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()
1403 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()
1453 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkDis()
1494 …N0_REG(REG_CLKGEN0_TS3_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS3_SHIFT)) >> (REG_CLKGEN0_TS3_SH… in HAL_TSP_TSIF_SelPad_ClkDis()
1546 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkDis()
H A DregTSP.h100 #define REG_CLKGEN0_TS3_SHIFT 8 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DhalTSP.c640 …S3_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_Power()
732 … = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_Power()
1161 …_TS3_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS3_SHIFT)) in HAL_TSP_TSIF_SelPad()
1162 … | (clk_src<<(REG_CLKGEN0_TS3_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT)); in HAL_TSP_TSIF_SelPad()
1480 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()
1500 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()
1550 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkDis()
1591 …N0_REG(REG_CLKGEN0_TS3_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS3_SHIFT)) >> (REG_CLKGEN0_TS3_SH… in HAL_TSP_TSIF_SelPad_ClkDis()
1643 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS3_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkDis()
H A DregTSP.h100 #define REG_CLKGEN0_TS3_SHIFT 8 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h104 #define REG_CLKGEN0_TS3_SHIFT 8 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h100 #define REG_CLKGEN0_TS3_SHIFT 8 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h100 #define REG_CLKGEN0_TS3_SHIFT 8 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h100 #define REG_CLKGEN0_TS3_SHIFT 8 macro