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Searched refs:REG_CLKGEN0_STC1_CW_SEL (Results 1 – 21 of 21) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h71 #define REG_CLKGEN0_STC1_CW_SEL 0x0200 macro
H A DhalTSP.c2285 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
2342 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
2423 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DhalTSP.c2728 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
2749 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
2800 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
H A DregTSP.h77 #define REG_CLKGEN0_STC1_CW_SEL 0x0200 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DhalTSP.c201 #define REG_CLKGEN0_STC1_CW_SEL 0x0200UL macro
3388 u32value = ((u32EngId == 0) ? REG_CLKGEN0_STC_CW_SEL : REG_CLKGEN0_STC1_CW_SEL); in HAL_TSP_Stc_ctrl()
3406 u32value = ((u32EngId == 0) ? REG_CLKGEN0_STC_CW_SEL : REG_CLKGEN0_STC1_CW_SEL); in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DhalTSP.c215 #define REG_CLKGEN0_STC1_CW_SEL 0x0200UL macro
3414 u32value = ((u32EngId == 0) ? REG_CLKGEN0_STC_CW_SEL : REG_CLKGEN0_STC1_CW_SEL); in HAL_TSP_Stc_ctrl()
3432 u32value = ((u32EngId == 0) ? REG_CLKGEN0_STC_CW_SEL : REG_CLKGEN0_STC1_CW_SEL); in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DhalTSP.c221 #define REG_CLKGEN0_STC1_CW_SEL 0x0002UL macro
3413 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH1) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
3419 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH1) |= REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DregTSP.h78 #define REG_CLKGEN0_STC1_CW_SEL 0x0200 macro
H A DhalTSP.c3632 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
3653 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
3704 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h78 #define REG_CLKGEN0_STC1_CW_SEL 0x0200 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c220 #define REG_CLKGEN0_STC1_CW_SEL 0x0200UL macro
3661 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
3667 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c220 #define REG_CLKGEN0_STC1_CW_SEL 0x0200UL macro
3644 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
3650 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c220 #define REG_CLKGEN0_STC1_CW_SEL 0x0200UL macro
3740 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
3746 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c220 #define REG_CLKGEN0_STC1_CW_SEL 0x0200UL macro
3701 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
3707 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h74 #define REG_CLKGEN0_STC1_CW_SEL 0x0200 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h74 #define REG_CLKGEN0_STC1_CW_SEL 0x0200 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h74 #define REG_CLKGEN0_STC1_CW_SEL 0x0200 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h74 #define REG_CLKGEN0_STC1_CW_SEL 0x0200 macro
H A DhalTSP.c3949 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
3982 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
4043 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DhalTSP.c3801 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
3822 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
3873 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
H A DregTSP.h74 #define REG_CLKGEN0_STC1_CW_SEL 0x0200 macro