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Searched refs:REG_CLKGEN0_DC0_STC1_CW_L (Results 1 – 21 of 21) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h76 #define REG_CLKGEN0_DC0_STC1_CW_L 0x08 macro
H A DhalTSP.c2297 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = 0x0000; in HAL_TSP_STC_Init()
2368 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L); in HAL_TSP_GetSTCSynth()
2426 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = u32Sync & 0xFFFF; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DhalTSP.c2734 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = 0x0000; in HAL_TSP_STC_Init()
2775 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L); in HAL_TSP_GetSTCSynth()
2803 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = u32Sync & 0xFFFF; in HAL_TSP_SetSTCSynth()
H A DregTSP.h81 #define REG_CLKGEN0_DC0_STC1_CW_L 0x08 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DhalTSP.c223 #define REG_CLKGEN0_DC0_STC1_CW_L 0x71UL macro
3379 … return (TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) | TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H)); in HAL_TSP_GetSTCSynth()
3414 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DregTSP.h82 #define REG_CLKGEN0_DC0_STC1_CW_L 0x08 macro
H A DhalTSP.c3638 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = 0x0000; in HAL_TSP_STC_Init()
3679 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L); in HAL_TSP_GetSTCSynth()
3707 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = u32Sync & 0xFFFF; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h82 #define REG_CLKGEN0_DC0_STC1_CW_L 0x08 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c224 #define REG_CLKGEN0_DC0_STC1_CW_L 0x07UL macro
3627 … return (TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) | TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H)); in HAL_TSP_GetSTCSynth()
3662 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c224 #define REG_CLKGEN0_DC0_STC1_CW_L 0x07UL macro
3610 … return (TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) | TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H)); in HAL_TSP_GetSTCSynth()
3645 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c224 #define REG_CLKGEN0_DC0_STC1_CW_L 0x07UL macro
3706 … return (TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) | TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H)); in HAL_TSP_GetSTCSynth()
3741 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c224 #define REG_CLKGEN0_DC0_STC1_CW_L 0x07UL macro
3667 … return (TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) | TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H)); in HAL_TSP_GetSTCSynth()
3702 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h79 #define REG_CLKGEN0_DC0_STC1_CW_L 0x08 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h79 #define REG_CLKGEN0_DC0_STC1_CW_L 0x08 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h79 #define REG_CLKGEN0_DC0_STC1_CW_L 0x08 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h79 #define REG_CLKGEN0_DC0_STC1_CW_L 0x08 macro
H A DhalTSP.c3957 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = 0x0000; in HAL_TSP_STC_Init()
4008 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L); in HAL_TSP_GetSTCSynth()
4046 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = u32Sync & 0xFFFF; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DhalTSP.c3807 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = 0x0000; in HAL_TSP_STC_Init()
3848 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L); in HAL_TSP_GetSTCSynth()
3876 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = u32Sync & 0xFFFF; in HAL_TSP_SetSTCSynth()
H A DregTSP.h79 #define REG_CLKGEN0_DC0_STC1_CW_L 0x08 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DhalTSP.c205 #define REG_CLKGEN0_DC0_STC1_CW_L 0x07UL macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DhalTSP.c219 #define REG_CLKGEN0_DC0_STC1_CW_L 0x07UL macro