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Searched refs:REG_CKG_ODCLK (Results 1 – 25 of 57) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A DhalPNL.c1423 …W2BYTEMSK(REG_CKG_ODCLK, CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // select source tobe LPLL clock in MHal_PNL_Init_XC_Clk()
1424 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1425 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h210 #define REG_CKG_ODCLK REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A DhalPNL.c1423 …W2BYTEMSK(REG_CKG_ODCLK, CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // select source tobe LPLL clock in MHal_PNL_Init_XC_Clk()
1424 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1425 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h210 #define REG_CKG_ODCLK REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/pnl/
H A DhalPNL.c710 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
711 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h215 #define REG_CKG_ODCLK REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/pnl/
H A DhalPNL.c710 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
711 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h215 #define REG_CKG_ODCLK REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/pnl/
H A DhalPNL.c710 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
711 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h215 #define REG_CKG_ODCLK REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/pnl/
H A DhalPNL.c710 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
711 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h215 #define REG_CKG_ODCLK REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A DhalPNL.c1763 …W2BYTEMSK(REG_CKG_ODCLK, CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // select source tobe LPLL clock in MHal_PNL_Init_XC_Clk()
1764 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1765 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A DhalPNL.c1763 …W2BYTEMSK(REG_CKG_ODCLK, CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // select source tobe LPLL clock in MHal_PNL_Init_XC_Clk()
1764 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1765 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/pws/hal/maldives/pws/
H A DregCLKGEN.h350 #define REG_CKG_ODCLK 0x1E37 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/k6/pws/
H A DregCLKGEN.h350 #define REG_CKG_ODCLK 0x1E37 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/macan/pws/
H A DregCLKGEN.h350 #define REG_CKG_ODCLK 0x1E37UL macro
/utopia/UTPA2-700.0.x/modules/pws/hal/mooney/pws/
H A DregCLKGEN.h350 #define REG_CKG_ODCLK 0x1E37UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.h246 #define REG_CKG_ODCLK REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A DhalPNL.h248 #define REG_CKG_ODCLK REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/pws/hal/messi/pws/
H A DregCLKGEN.h350 #define REG_CKG_ODCLK 0x1E37UL macro
/utopia/UTPA2-700.0.x/modules/pws/hal/manhattan/pws/
H A DregCLKGEN.h350 #define REG_CKG_ODCLK 0x1E37UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A DhalPNL.h223 #define REG_CKG_ODCLK REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A DhalPNL.h248 #define REG_CKG_ODCLK REG_CLKGEN0_53_L macro
/utopia/UTPA2-700.0.x/modules/pws/hal/k6lite/pws/
H A DregCLKGEN.h350 #define REG_CKG_ODCLK 0x1E37 macro

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