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Searched refs:MIU0_REG_SEL0 (Results 1 – 25 of 126) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/hvd/
H A DhalHVD_sub.c210 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
1350 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) == BIT(13)) ) in HAL_HVD_Sub_CheckMIUSel()
1352 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) ); in HAL_HVD_Sub_CheckMIUSel()
1356 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(13), BIT(13)); in HAL_HVD_Sub_CheckMIUSel()
1361 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) == BIT(7)) ) in HAL_HVD_Sub_CheckMIUSel()
1363 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) ); in HAL_HVD_Sub_CheckMIUSel()
1367 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(7), BIT(7)); in HAL_HVD_Sub_CheckMIUSel()
1370 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) == BIT(8)) ) in HAL_HVD_Sub_CheckMIUSel()
1372 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) ); in HAL_HVD_Sub_CheckMIUSel()
1376 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(8), BIT(8)); in HAL_HVD_Sub_CheckMIUSel()
[all …]
H A DhalHVD.c215 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
1448 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) == BIT(13)) ) in HAL_HVD_CheckMIUSel()
1450 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) ); in HAL_HVD_CheckMIUSel()
1454 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(13), BIT(13)); in HAL_HVD_CheckMIUSel()
1459 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) == BIT(7)) ) in HAL_HVD_CheckMIUSel()
1461 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) ); in HAL_HVD_CheckMIUSel()
1465 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(7), BIT(7)); in HAL_HVD_CheckMIUSel()
1468 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) == BIT(8)) ) in HAL_HVD_CheckMIUSel()
1470 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) ); in HAL_HVD_CheckMIUSel()
1474 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(8), BIT(8)); in HAL_HVD_CheckMIUSel()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/hvd/
H A DhalHVD_sub.c210 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
1350 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) == BIT(13)) ) in HAL_HVD_Sub_CheckMIUSel()
1352 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) ); in HAL_HVD_Sub_CheckMIUSel()
1356 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(13), BIT(13)); in HAL_HVD_Sub_CheckMIUSel()
1361 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) == BIT(7)) ) in HAL_HVD_Sub_CheckMIUSel()
1363 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) ); in HAL_HVD_Sub_CheckMIUSel()
1367 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(7), BIT(7)); in HAL_HVD_Sub_CheckMIUSel()
1370 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) == BIT(8)) ) in HAL_HVD_Sub_CheckMIUSel()
1372 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) ); in HAL_HVD_Sub_CheckMIUSel()
1376 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(8), BIT(8)); in HAL_HVD_Sub_CheckMIUSel()
[all …]
H A DhalHVD.c215 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
1448 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) == BIT(13)) ) in HAL_HVD_CheckMIUSel()
1450 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) ); in HAL_HVD_CheckMIUSel()
1454 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(13), BIT(13)); in HAL_HVD_CheckMIUSel()
1459 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) == BIT(7)) ) in HAL_HVD_CheckMIUSel()
1461 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) ); in HAL_HVD_CheckMIUSel()
1465 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(7), BIT(7)); in HAL_HVD_CheckMIUSel()
1468 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) == BIT(8)) ) in HAL_HVD_CheckMIUSel()
1470 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) ); in HAL_HVD_CheckMIUSel()
1474 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(8), BIT(8)); in HAL_HVD_CheckMIUSel()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/hvd/
H A DhalHVD_sub.c210 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
1350 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) == BIT(13)) ) in HAL_HVD_Sub_CheckMIUSel()
1352 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) ); in HAL_HVD_Sub_CheckMIUSel()
1356 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(13), BIT(13)); in HAL_HVD_Sub_CheckMIUSel()
1361 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) == BIT(7)) ) in HAL_HVD_Sub_CheckMIUSel()
1363 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) ); in HAL_HVD_Sub_CheckMIUSel()
1367 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(7), BIT(7)); in HAL_HVD_Sub_CheckMIUSel()
1370 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) == BIT(8)) ) in HAL_HVD_Sub_CheckMIUSel()
1372 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) ); in HAL_HVD_Sub_CheckMIUSel()
1376 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(8), BIT(8)); in HAL_HVD_Sub_CheckMIUSel()
[all …]
H A DhalHVD.c215 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
1448 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) == BIT(13)) ) in HAL_HVD_CheckMIUSel()
1450 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) ); in HAL_HVD_CheckMIUSel()
1454 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(13), BIT(13)); in HAL_HVD_CheckMIUSel()
1459 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) == BIT(7)) ) in HAL_HVD_CheckMIUSel()
1461 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) ); in HAL_HVD_CheckMIUSel()
1465 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(7), BIT(7)); in HAL_HVD_CheckMIUSel()
1468 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) == BIT(8)) ) in HAL_HVD_CheckMIUSel()
1470 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) ); in HAL_HVD_CheckMIUSel()
1474 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(8), BIT(8)); in HAL_HVD_CheckMIUSel()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/hvd/
H A DhalHVD_sub.c210 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
1350 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) == BIT(13)) ) in HAL_HVD_Sub_CheckMIUSel()
1352 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) ); in HAL_HVD_Sub_CheckMIUSel()
1356 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(13), BIT(13)); in HAL_HVD_Sub_CheckMIUSel()
1361 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) == BIT(7)) ) in HAL_HVD_Sub_CheckMIUSel()
1363 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) ); in HAL_HVD_Sub_CheckMIUSel()
1367 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(7), BIT(7)); in HAL_HVD_Sub_CheckMIUSel()
1370 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) == BIT(8)) ) in HAL_HVD_Sub_CheckMIUSel()
1372 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) ); in HAL_HVD_Sub_CheckMIUSel()
1376 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(8), BIT(8)); in HAL_HVD_Sub_CheckMIUSel()
[all …]
H A DhalHVD.c215 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
1448 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) == BIT(13)) ) in HAL_HVD_CheckMIUSel()
1450 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) ); in HAL_HVD_CheckMIUSel()
1454 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(13), BIT(13)); in HAL_HVD_CheckMIUSel()
1459 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) == BIT(7)) ) in HAL_HVD_CheckMIUSel()
1461 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) ); in HAL_HVD_CheckMIUSel()
1465 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(7), BIT(7)); in HAL_HVD_CheckMIUSel()
1468 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) == BIT(8)) ) in HAL_HVD_CheckMIUSel()
1470 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) ); in HAL_HVD_CheckMIUSel()
1474 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(8), BIT(8)); in HAL_HVD_CheckMIUSel()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/hvd/
H A DhalHVD_sub.c210 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
1350 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) == BIT(13)) ) in HAL_HVD_Sub_CheckMIUSel()
1352 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) ); in HAL_HVD_Sub_CheckMIUSel()
1356 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(13), BIT(13)); in HAL_HVD_Sub_CheckMIUSel()
1361 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) == BIT(7)) ) in HAL_HVD_Sub_CheckMIUSel()
1363 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) ); in HAL_HVD_Sub_CheckMIUSel()
1367 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(7), BIT(7)); in HAL_HVD_Sub_CheckMIUSel()
1370 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) == BIT(8)) ) in HAL_HVD_Sub_CheckMIUSel()
1372 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) ); in HAL_HVD_Sub_CheckMIUSel()
1376 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(8), BIT(8)); in HAL_HVD_Sub_CheckMIUSel()
[all …]
H A DhalHVD.c215 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
1448 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) == BIT(13)) ) in HAL_HVD_CheckMIUSel()
1450 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) ); in HAL_HVD_CheckMIUSel()
1454 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(13), BIT(13)); in HAL_HVD_CheckMIUSel()
1459 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) == BIT(7)) ) in HAL_HVD_CheckMIUSel()
1461 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) ); in HAL_HVD_CheckMIUSel()
1465 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(7), BIT(7)); in HAL_HVD_CheckMIUSel()
1468 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) == BIT(8)) ) in HAL_HVD_CheckMIUSel()
1470 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) ); in HAL_HVD_CheckMIUSel()
1474 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(8), BIT(8)); in HAL_HVD_CheckMIUSel()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/hvd/
H A DhalHVD_sub.c210 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
1350 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) == BIT(13)) ) in HAL_HVD_Sub_CheckMIUSel()
1352 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) ); in HAL_HVD_Sub_CheckMIUSel()
1356 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(13), BIT(13)); in HAL_HVD_Sub_CheckMIUSel()
1361 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) == BIT(7)) ) in HAL_HVD_Sub_CheckMIUSel()
1363 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) ); in HAL_HVD_Sub_CheckMIUSel()
1367 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(7), BIT(7)); in HAL_HVD_Sub_CheckMIUSel()
1370 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) == BIT(8)) ) in HAL_HVD_Sub_CheckMIUSel()
1372 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) ); in HAL_HVD_Sub_CheckMIUSel()
1376 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(8), BIT(8)); in HAL_HVD_Sub_CheckMIUSel()
[all …]
H A DhalHVD.c215 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
1448 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) == BIT(13)) ) in HAL_HVD_CheckMIUSel()
1450 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) ); in HAL_HVD_CheckMIUSel()
1454 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(13), BIT(13)); in HAL_HVD_CheckMIUSel()
1459 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) == BIT(7)) ) in HAL_HVD_CheckMIUSel()
1461 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) ); in HAL_HVD_CheckMIUSel()
1465 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(7), BIT(7)); in HAL_HVD_CheckMIUSel()
1468 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) == BIT(8)) ) in HAL_HVD_CheckMIUSel()
1470 …fAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) ); in HAL_HVD_CheckMIUSel()
1474 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(8), BIT(8)); in HAL_HVD_CheckMIUSel()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/
H A DhalVPU_EX.c273 …(((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(5)) == 0))…
274 …(((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) ==…
277 …(((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(5)) == 0))…
278 …(((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) ==…
281 …(((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(3)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(3)) == 0))…
282 …(((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(7)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(7)) == 0)))
285 …(((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == BIT(5)) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(5)) =…
286 …(((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0…
289 …(((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == BIT(5)) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(5)) =…
290 …(((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0…
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DhalVPU_EX.c242 #define VPU_D_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0)
243 #define VPU_Q_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0)
244 #define VPU_I_R_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0)
245 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == BIT(5))
246 #define VPU_Q_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == BIT(5))
247 #define VPU_I_R_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
257 #define VPU_D_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0)
258 #define VPU_Q_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0)
259 #define VPU_I_R_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0)
260 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == BIT(5))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DhalVPU_EX.c242 #define VPU_D_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0)
243 #define VPU_Q_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0)
244 #define VPU_I_R_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0)
245 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == BIT(5))
246 #define VPU_Q_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == BIT(5))
247 #define VPU_I_R_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
257 #define VPU_D_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0)
258 #define VPU_Q_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0)
259 #define VPU_I_R_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0)
260 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == BIT(5))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/vpu/
H A DhalVPU.c133 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
134 #define VPU_Q_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
135 #define VPU_I_R_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) //g08
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/vpu/
H A DhalVPU.c133 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
134 #define VPU_Q_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
135 #define VPU_I_R_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) //g08
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/vpu/
H A DhalVPU.c133 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
134 #define VPU_Q_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
135 #define VPU_I_R_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) //g08
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/vpu/
H A DhalVPU.c133 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
134 #define VPU_Q_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
135 #define VPU_I_R_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) //g08
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/vpu/
H A DhalVPU.c133 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
134 #define VPU_Q_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
135 #define VPU_I_R_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) //g08
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/vpu/
H A DhalVPU.c133 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
134 #define VPU_Q_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
135 #define VPU_I_R_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) //g08
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A DhalVPU_EX.c262 #define VPU_D_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadB…
263 #define VPU_Q_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadB…
264 #define VPU_I_R_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_Rea…
265 #define VPU_D_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6)) && ((_VPU_…
266 #define VPU_Q_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6)) && ((_VPU_…
267 #define VPU_I_R_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) && ((_VP…
268 #define VPU_D_RW_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadB…
269 #define VPU_Q_RW_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadB…
270 #define VPU_I_R_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_Rea…
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A DhalVPU_EX.c254 #define VPU_D_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadB…
255 #define VPU_Q_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadB…
256 #define VPU_I_R_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_Rea…
257 #define VPU_D_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6)) && ((_VPU_…
258 #define VPU_Q_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6)) && ((_VPU_…
259 #define VPU_I_R_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) && ((_VP…
260 #define VPU_D_RW_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadB…
261 #define VPU_Q_RW_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadB…
262 #define VPU_I_R_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_Rea…
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DhalVPU_EX.c267 #define VPU_D_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadB…
268 #define VPU_Q_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadB…
269 #define VPU_I_R_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_Rea…
270 #define VPU_D_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6)) && ((_VPU_…
271 #define VPU_Q_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6)) && ((_VPU_…
272 #define VPU_I_R_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) && ((_VP…
273 #define VPU_D_RW_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadB…
274 #define VPU_Q_RW_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadB…
275 #define VPU_I_R_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_Rea…
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DhalVPU_EX.c268 #define VPU_D_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadB…
269 #define VPU_Q_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadB…
270 #define VPU_I_R_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_Rea…
271 #define VPU_D_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6)) && ((_VPU_…
272 #define VPU_Q_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6)) && ((_VPU_…
273 #define VPU_I_R_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) && ((_VP…
274 #define VPU_D_RW_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadB…
275 #define VPU_Q_RW_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadB…
276 #define VPU_I_R_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_Rea…

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