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Searched refs:MHal_HDMITxPM_Mask_Write (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/
H A DhalHDMITx.c635 … MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, u16reg_val); // GPIO_PM mask in MHal_HDMITx_Int_Disable()
660 …MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_P… in MHal_HDMITx_Int_Enable()
661 … MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, 0); // GPIO_PM non-mask in MHal_HDMITx_Int_Enable()
685 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, u16reg_val); in MHal_HDMITx_Int_Clear()
686 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, 0); in MHal_HDMITx_Int_Clear()
H A DhalHDMIUtilTx.c833 void MHal_HDMITxPM_Mask_Write(MS_U32 bank, MS_U16 address, MS_U16 reg_mask, MS_U16 reg_data) in MHal_HDMITxPM_Mask_Write() function
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/
H A DhalHDMITx.c658 … MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, u16reg_val); // GPIO_PM mask in MHal_HDMITx_Int_Disable()
683 …MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_P… in MHal_HDMITx_Int_Enable()
684 … MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, 0); // GPIO_PM non-mask in MHal_HDMITx_Int_Enable()
708 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, u16reg_val); in MHal_HDMITx_Int_Clear()
709 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, 0); in MHal_HDMITx_Int_Clear()
H A DhalHDMIUtilTx.c833 void MHal_HDMITxPM_Mask_Write(MS_U32 bank, MS_U16 address, MS_U16 reg_mask, MS_U16 reg_data) in MHal_HDMITxPM_Mask_Write() function
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/
H A DhalHDMITx.c684 … MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, u16reg_val); // GPIO_PM mask in MHal_HDMITx_Int_Disable()
709 …MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_P… in MHal_HDMITx_Int_Enable()
710 … MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, 0); // GPIO_PM non-mask in MHal_HDMITx_Int_Enable()
734 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, u16reg_val); in MHal_HDMITx_Int_Clear()
735 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, 0); in MHal_HDMITx_Int_Clear()
H A DhalHDMIUtilTx.c833 void MHal_HDMITxPM_Mask_Write(MS_U32 bank, MS_U16 address, MS_U16 reg_mask, MS_U16 reg_data) in MHal_HDMITxPM_Mask_Write() function
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/
H A DhalHDMITx.c672 … MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, u16reg_val); // GPIO_PM mask in MHal_HDMITx_Int_Disable()
697 …MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_P… in MHal_HDMITx_Int_Enable()
698 … MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, 0); // GPIO_PM non-mask in MHal_HDMITx_Int_Enable()
722 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, u16reg_val); in MHal_HDMITx_Int_Clear()
723 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, 0); in MHal_HDMITx_Int_Clear()
H A DhalHDMIUtilTx.c833 void MHal_HDMITxPM_Mask_Write(MS_U32 bank, MS_U16 address, MS_U16 reg_mask, MS_U16 reg_data) in MHal_HDMITxPM_Mask_Write() function
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/
H A DhalHDMITx.c806 … MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, u16reg_val); // GPIO_PM mask in MHal_HDMITx_Int_Disable()
831 …MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_P… in MHal_HDMITx_Int_Enable()
832 … MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, 0); // GPIO_PM non-mask in MHal_HDMITx_Int_Enable()
856 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, u16reg_val); in MHal_HDMITx_Int_Clear()
857 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, 0); in MHal_HDMITx_Int_Clear()
H A DhalHDMIUtilTx.c833 void MHal_HDMITxPM_Mask_Write(MS_U32 bank, MS_U16 address, MS_U16 reg_mask, MS_U16 reg_data) in MHal_HDMITxPM_Mask_Write() function
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/
H A DhalHDMITx.c861 … MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, u16reg_val); // GPIO_PM mask in MHal_HDMITx_Int_Disable()
886 …MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_P… in MHal_HDMITx_Int_Enable()
887 … MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, 0); // GPIO_PM non-mask in MHal_HDMITx_Int_Enable()
911 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, u16reg_val); in MHal_HDMITx_Int_Clear()
912 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, 0); in MHal_HDMITx_Int_Clear()
H A DhalHDMIUtilTx.c833 void MHal_HDMITxPM_Mask_Write(MS_U32 bank, MS_U16 address, MS_U16 reg_mask, MS_U16 reg_data) in MHal_HDMITxPM_Mask_Write() function
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/include/
H A DhalHDMIUtilTx.h209 INTERFACE void MHal_HDMITxPM_Mask_Write(MS_U32 bank, MS_U16 address, MS_U16 reg_mask, MS_U16 reg_da…
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/include/
H A DhalHDMIUtilTx.h209 INTERFACE void MHal_HDMITxPM_Mask_Write(MS_U32 bank, MS_U16 address, MS_U16 reg_mask, MS_U16 reg_da…
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/include/
H A DhalHDMIUtilTx.h209 INTERFACE void MHal_HDMITxPM_Mask_Write(MS_U32 bank, MS_U16 address, MS_U16 reg_mask, MS_U16 reg_da…
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/include/
H A DhalHDMIUtilTx.h209 INTERFACE void MHal_HDMITxPM_Mask_Write(MS_U32 bank, MS_U16 address, MS_U16 reg_mask, MS_U16 reg_da…
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/include/
H A DhalHDMIUtilTx.h209 INTERFACE void MHal_HDMITxPM_Mask_Write(MS_U32 bank, MS_U16 address, MS_U16 reg_mask, MS_U16 reg_da…
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/include/
H A DhalHDMIUtilTx.h209 INTERFACE void MHal_HDMITxPM_Mask_Write(MS_U32 bank, MS_U16 address, MS_U16 reg_mask, MS_U16 reg_da…