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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 ///////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file halHDMIUtilTx.h 98 /// @author MStar Semiconductor,Inc. 99 /// @brief HDMITx Utility HAL 100 ///////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _HAL_HDMIUTILTX_H_ 103 #define _HAL_HDMIUTILTX_H_ 104 105 106 #ifdef __cplusplus 107 extern "C" 108 { 109 #endif 110 111 //------------------------------------------------------------------------------------------------- 112 // Hardware Capability 113 //------------------------------------------------------------------------------------------------- 114 115 116 //------------------------------------------------------------------------------------------------- 117 // Macro and Define 118 //------------------------------------------------------------------------------------------------- 119 120 #define BIT0 0x0001U 121 #define BIT1 0x0002U 122 #define BIT2 0x0004U 123 #define BIT3 0x0008U 124 #define BIT4 0x0010U 125 #define BIT5 0x0020U 126 #define BIT6 0x0040U 127 #define BIT7 0x0080U 128 #define BIT8 0x0100U 129 #define BIT9 0x0200U 130 #define BIT10 0x0400U 131 #define BIT11 0x0800U 132 #define BIT12 0x1000U 133 #define BIT13 0x2000U 134 #define BIT14 0x4000U 135 #define BIT15 0x8000U 136 137 //------------------------------------------------------------------------------------------------- 138 // Type and Structure 139 //------------------------------------------------------------------------------------------------- 140 141 typedef struct 142 { 143 MS_U32 bank; 144 MS_U16 address; 145 MS_U16 mask; 146 MS_U16 value; 147 } MSTHDMITX_REG_TYPE; 148 149 150 /////////////Wilson:: for Kano, HDMITX 2.0 architecture @20150702 151 typedef enum 152 { 153 E_SCDC_SINK_VER_IDX = 0x01, 154 E_SCDC_SRC_VER_IDX = 0x02, 155 E_SCDC_UPDATE_0_IDX = 0x10, 156 E_SCDC_UPDATE_1_IDX= 0x11, 157 E_SCDC_TMDS_CONFIG_IDX = 0x20, 158 E_SCDC_SCRAMBLE_STAT_IDX = 0x21, 159 E_SCDC_CONFIG_0_IDX = 0x30, 160 E_SCDC_STATFLAG_0_IDX = 0x40, 161 E_SCDC_STATFLAG_1_IDX = 0x41, 162 E_SCDC_ERR_DET_START_IDX = 0x50, 163 E_SCDC_ERR_DET_CHKSUM_IDX = 0x56, 164 E_SCDC_TEST_CONFIG_0_IDX = 0xC0, 165 E_SCDC_MANUFACTURER_OUI_IDX = 0xD0, 166 E_SCDC_DEVICE_ID_IDX = 0xD3, 167 E_SCDC_MANUFACTURER_SPEC_IDX = 0xDE 168 } enMsHDMITX_SCDC_FIELD_OFFSET_LIST; 169 170 171 //------------------------------------------------------------------------------------------------- 172 // Function and Variable 173 //------------------------------------------------------------------------------------------------- 174 175 #ifdef MHAL_HDMIUTILTX_C 176 #define INTERFACE 177 #else 178 #define INTERFACE extern 179 #endif 180 181 #if (defined(MSOS_TYPE_LINUX_KERNEL)) 182 INTERFACE void MHal_HDMITx_SetIOMapBase(MS_VIRT u32Base, MS_VIRT u32PMBase, MS_VIRT u32CoproBase); 183 #else 184 INTERFACE void MHal_HDMITx_SetIOMapBase(MS_VIRT u32Base, MS_VIRT u32PMBase); 185 #endif 186 187 INTERFACE MS_BOOL MHal_HDMITx_Rx74WriteByte(MS_U8 addr, MS_U8 value); 188 189 INTERFACE MS_BOOL MHal_HDMITx_Rx74ReadByte(MS_U8 addr, MS_U8 *pBuf); 190 191 INTERFACE MS_BOOL MHal_HDMITx_Rx74WriteBytes(MS_U8 addr, MS_U16 len, MS_U8 *buf); 192 193 INTERFACE MS_BOOL MHal_HDMITx_Rx74ReadBytes(MS_U8 addr, MS_U16 len, MS_U8 *buf); 194 195 INTERFACE MS_BOOL MHal_HDMITx_EdidReadBlock(MS_U8 num, MS_U8 *buf); 196 197 INTERFACE MS_U16 MHal_HDMITx_Read(MS_U32 bank, MS_U16 address); 198 199 INTERFACE void MHal_HDMITx_Write(MS_U32 bank, MS_U16 address, MS_U16 reg_data); 200 201 INTERFACE void MHal_HDMITx_Mask_Write(MS_U32 bank, MS_U16 address, MS_U16 reg_mask, MS_U16 reg_data); 202 203 INTERFACE void MHal_HDMITx_RegsTbl_Write(MSTHDMITX_REG_TYPE *pTable, MS_U8 num); 204 205 INTERFACE MS_U16 MHal_HDMITxPM_Read(MS_U32 bank, MS_U16 address); 206 207 INTERFACE void MHal_HDMITxPM_Write(MS_U32 bank, MS_U16 address, MS_U16 reg_data); 208 209 INTERFACE void MHal_HDMITxPM_Mask_Write(MS_U32 bank, MS_U16 address, MS_U16 reg_mask, MS_U16 reg_data); 210 211 // Read HDCP key from external EEPROM if not used internal HDCP key 212 INTERFACE MS_BOOL MHal_HDMITx_HDCPKeyReadByte(MS_U32 u32Addr, MS_U8 *pu8Buf, MS_U32 u32Size); 213 214 INTERFACE void MHal_HDMITx_UtilDebugEnable(MS_BOOL benable); 215 216 INTERFACE MS_U32 MHal_HDMITx_GetDDCDelayCount(void); 217 INTERFACE void MHal_HDMITx_SetDDCDelayCount(MS_U32 u32Delay); 218 INTERFACE MS_BOOL MHal_HDMITx_AdjustDDCFreq(MS_U32 u32Speed_K); 219 220 //SCDC 221 INTERFACE void Mhal_HDMITx_SCDCSetTmdsConfig(MS_BOOL bClkRatio, MS_BOOL bScrambleEn); 222 INTERFACE MS_BOOL Mhal_HDMITx_SCDCAccessField(enMsHDMITX_SCDC_FIELD_OFFSET_LIST enField, MS_BOOL bReadAction, MS_U8* pucData, MS_U8 ucLen); 223 224 #ifdef __cplusplus 225 } 226 #endif 227 228 #endif // _HAL_HDMIUTILTX_H_ 229 230