Searched refs:E_DMD_DVBC_CFG_TS_CLK_INV (Results 1 – 8 of 8) sorted by relevance
| /utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/ |
| H A D | halDMD_INTERN_DVBC.c | 1422 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0); in INTERN_DVBC_Serial_Control()
1424 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1); in INTERN_DVBC_Serial_Control()
1464 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0); in INTERN_DVBC_Serial_Control()
1466 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1); in INTERN_DVBC_Serial_Control()
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| /utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/ |
| H A D | halDMD_INTERN_DVBC.c | 1366 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0); in INTERN_DVBC_Serial_Control()
1368 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1); in INTERN_DVBC_Serial_Control()
1408 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0); in INTERN_DVBC_Serial_Control()
1410 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1); in INTERN_DVBC_Serial_Control()
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| /utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/ |
| H A D | halDMD_INTERN_DVBC.c | 1376 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0); in INTERN_DVBC_Serial_Control()
1378 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1); in INTERN_DVBC_Serial_Control()
1418 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0); in INTERN_DVBC_Serial_Control()
1420 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1); in INTERN_DVBC_Serial_Control()
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| /utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/ |
| H A D | halDMD_INTERN_DVBC.c | 1171 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0); in INTERN_DVBC_Serial_Control()
1173 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1); in INTERN_DVBC_Serial_Control()
1211 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0); in INTERN_DVBC_Serial_Control()
1213 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1); in INTERN_DVBC_Serial_Control()
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| /utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/ |
| H A D | halDMD_INTERN_DVBC.c | 1357 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0); in INTERN_DVBC_Serial_Control()
1359 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1); in INTERN_DVBC_Serial_Control()
1399 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0); in INTERN_DVBC_Serial_Control()
1401 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1); in INTERN_DVBC_Serial_Control()
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| /utopia/UTPA2-700.0.x/projects/tmplib/include/ |
| H A D | drvDMD_INTERN_DVBC.h | 344 E_DMD_DVBC_CFG_TS_CLK_INV, enumerator
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| /utopia/UTPA2-700.0.x/mxlib/include/ |
| H A D | drvDMD_INTERN_DVBC.h | 263 E_DMD_DVBC_CFG_TS_CLK_INV, enumerator
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| /utopia/UTPA2-700.0.x/projects/build/ |
| H A D | preprocess.txt | 55495 E_DMD_DVBC_CFG_TS_CLK_INV,
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