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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvDMD_INTERN_DVBC.h 98 /// @brief DVBC Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _DRV_DVBC_H_ 103 #define _DRV_DVBC_H_ 104 105 #include "MsTypes.h" 106 107 #include "MsCommon.h" 108 #include "drvDMD_common.h" 109 #include "UFO.h" 110 #ifdef __cplusplus 111 extern "C" 112 { 113 #endif 114 115 116 //------------------------------------------------------------------------------------------------- 117 // Driver Capability 118 //------------------------------------------------------------------------------------------------- 119 120 121 //------------------------------------------------------------------------------------------------- 122 // Macro and Define 123 //------------------------------------------------------------------------------------------------- 124 #define MSIF_DMD_DVBC_INTERN_LIB_CODE {'D','V', 'B','C'} //Lib code 125 #define MSIF_DMD_DVBC_INTERN_LIBVER {'0','1'} //LIB version 126 #define MSIF_DMD_DVBC_INTERN_BUILDNUM {'2','2' } //Build Number 127 #define MSIF_DMD_DVBC_INTERN_CHANGELIST {'0','0','0','0','0','0','0','0'} //P4 ChangeList Number 128 // oga 129 #define INDEX_C_TS_PHASE_EN 23 130 #define INDEX_C_TS_PHASE_NUM 24 131 132 #define DMD_DVBC_INTERN_VER /* Character String for DRV/API version */ \ 133 MSIF_TAG, /* 'MSIF' */ \ 134 MSIF_CLASS, /* '00' */ \ 135 MSIF_CUS, /* 0x0000 */ \ 136 MSIF_MOD, /* 0x0000 */ \ 137 MSIF_CHIP, \ 138 MSIF_CPU, \ 139 MSIF_DMD_DVBC_INTERN_LIB_CODE, /* IP__ */ \ 140 MSIF_DMD_DVBC_INTERN_LIBVER, /* 0.0 ~ Z.Z */ \ 141 MSIF_DMD_DVBC_INTERN_BUILDNUM, /* 00 ~ 99 */ \ 142 MSIF_DMD_DVBC_INTERN_CHANGELIST, /* CL# */ \ 143 MSIF_OS 144 145 #define IS_BITS_SET(val, bits) (((val)&(bits)) == (bits)) 146 147 //------------------------------------------------------------------------------------------------- 148 // Type and Structure 149 //------------------------------------------------------------------------------------------------- 150 typedef enum 151 { 152 DMD_DVBC_DBGLV_NONE, // disable all the debug message 153 DMD_DVBC_DBGLV_INFO, // information 154 DMD_DVBC_DBGLV_NOTICE, // normal but significant condition 155 DMD_DVBC_DBGLV_WARNING, // warning conditions 156 DMD_DVBC_DBGLV_ERR, // error conditions 157 DMD_DVBC_DBGLV_CRIT, // critical conditions 158 DMD_DVBC_DBGLV_ALERT, // action must be taken immediately 159 DMD_DVBC_DBGLV_EMERG, // system is unusable 160 DMD_DVBC_DBGLV_DEBUG, // debug-level messages 161 } DMD_DVBC_DbgLv; 162 163 typedef enum 164 { 165 DMD_DVBC_LOCK, 166 DMD_DVBC_CHECKING, 167 DMD_DVBC_CHECKEND, 168 DMD_DVBC_UNLOCK, 169 DMD_DVBC_NULL, 170 } DMD_DVBC_LOCK_STATUS; 171 172 typedef enum 173 { 174 DMD_DVBC_GETLOCK, 175 DMD_DVBC_GETLOCK_FEC_LOCK, 176 DMD_DVBC_GETLOCK_PSYNC_LOCK, 177 DMD_DVBC_GETLOCK_TPS_LOCK, 178 DMD_DVBC_GETLOCK_DCR_LOCK, 179 DMD_DVBC_GETLOCK_AGC_LOCK, 180 DMD_DVBC_GETLOCK_MODE_DET, 181 DMD_DVBC_GETLOCK_NO_CHANNEL, 182 DMD_DVBC_GETLOCK_ATV_DETECT, 183 DMD_DVBC_GETLOCK_TR_LOCK, 184 DMD_DVBC_GETLOCK_TR_EVER_LOCK, 185 // DMD_DVBC_GETLOCK_FEC_STABLE_LOCK, 186 } DMD_DVBC_GETLOCK_TYPE; 187 188 typedef enum 189 { 190 DMD_DVBC_QAM16 = 0, 191 DMD_DVBC_QAM32 = 1, 192 DMD_DVBC_QAM64 = 2, 193 DMD_DVBC_QAM128 = 3, 194 DMD_DVBC_QAM256 = 4, 195 DMD_DVBC_QAMAUTO = 128, 196 } DMD_DVBC_MODULATION_TYPE; 197 198 typedef enum 199 { 200 DMD_DVBC_RF_CH_BAND_6MHz = 0x01, 201 DMD_DVBC_RF_CH_BAND_7MHz = 0x02, 202 DMD_DVBC_RF_CH_BAND_8MHz = 0x03, 203 DMD_DVBC_RF_CH_BAND_INVALID 204 } DMD_DVBC_RF_CHANNEL_BANDWIDTH; 205 206 typedef enum 207 { 208 E_DMD_DVBC_PARAM_VERSION, //0x00 209 E_DMD_DVBC_OP_RFAGC_EN, 210 E_DMD_DVBC_OP_HUMDET_EN, 211 E_DMD_DVBC_OP_DCR_EN, 212 E_DMD_DVBC_OP_IQB_EN, 213 E_DMD_DVBC_OP_AUTO_IQ, 214 E_DMD_DVBC_OP_AUTO_RFMAX, 215 E_DMD_DVBC_OP_AUTO_ACI, 216 E_DMD_DVBC_OP_AUTO_SCAN, 217 E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 218 E_DMD_DVBC_OP_AUTO_SCAN_QAM, 219 E_DMD_DVBC_OP_ATV_DETECTOR_EN, 220 E_DMD_DVBC_OP_ZIF_EN, //ZIF 221 E_DMD_DVBC_OP_NORMALIF_EN, //NIF 222 E_DMD_DVBC_OP_LIF_EN, //LIF 223 E_DMD_DVBC_OP_SAWLESS_EN, //SAWLESS 224 E_DMD_DVBC_IF_INV_PWM_OUT_EN, //Sony Tuner , 0x10 225 E_DMD_DVBC_CFG_RSSI, 226 E_DMD_DVBC_CFG_ZIF, 227 E_DMD_DVBC_CFG_FS_L, //FS 228 E_DMD_DVBC_CFG_FS_H, //FS 229 E_DMD_DVBC_CFG_FIF_L, //IF 230 E_DMD_DVBC_CFG_FIF_H, //IF 231 E_DMD_DVBC_CFG_FC_L, //FC 232 E_DMD_DVBC_CFG_FC_H, //FC 233 E_DMD_DVBC_CFG_BW0_L, 234 E_DMD_DVBC_CFG_BW0_H, 235 E_DMD_DVBC_CFG_BW1_L, 236 E_DMD_DVBC_CFG_BW1_H, 237 E_DMD_DVBC_CFG_BW2_L, 238 E_DMD_DVBC_CFG_BW2_H, 239 E_DMD_DVBC_CFG_BW3_L, 240 E_DMD_DVBC_CFG_BW3_H, //0x20 241 E_DMD_DVBC_CFG_BW4_L, 242 E_DMD_DVBC_CFG_BW4_H, 243 E_DMD_DVBC_CFG_BW5_L, 244 E_DMD_DVBC_CFG_BW5_H, 245 E_DMD_DVBC_CFG_BW6_L, 246 E_DMD_DVBC_CFG_BW6_H, 247 E_DMD_DVBC_CFG_BW7_L, 248 E_DMD_DVBC_CFG_BW7_H, 249 E_DMD_DVBC_CFG_BW8_L, 250 E_DMD_DVBC_CFG_BW8_H, 251 E_DMD_DVBC_CFG_BW9_L, 252 E_DMD_DVBC_CFG_BW9_H, 253 E_DMD_DVBC_CFG_BW10_L, 254 E_DMD_DVBC_CFG_BW10_H, 255 E_DMD_DVBC_CFG_BW11_L, 256 E_DMD_DVBC_CFG_BW11_H, //0x30 257 E_DMD_DVBC_CFG_RFMAX, 258 E_DMD_DVBC_CFG_QAM, 259 E_DMD_DVBC_CFG_IQ_SWAP, 260 E_DMD_DVBC_CFG_CCI, 261 E_DMD_DVBC_CFG_TS_SERIAL, 262 E_DMD_DVBC_CFG_TS_CLK_RATE, 263 E_DMD_DVBC_CFG_TS_CLK_INV, 264 E_DMD_DVBC_CFG_TS_DATA_SWAP, 265 E_DMD_DVBC_CFG_TS_EN, 266 E_DMD_DVBC_AGC_REF_L, 267 E_DMD_DVBC_AGC_REF_H, 268 E_DMD_DVBC_AGC_K, 269 E_DMD_DVBC_AGC_LOCK_TH, 270 E_DMD_DVBC_AGC_LOCK_NUM, 271 E_DMD_DVBC_ADC_PGA_GAIN_I, 272 E_DMD_DVBC_ADC_PGA_GAIN_Q, //0x40 273 E_DMD_DVBC_ADC_PWDN_I, 274 E_DMD_DVBC_ADC_PWDN_Q, 275 E_DMD_DVBC_ADC_MPLL_DIV_SEL, 276 E_DMD_DVBC_CCI_BYPASS, 277 E_DMD_DVBC_CCI_LOCK_DET, 278 E_DMD_DVBC_CCI_FREQN_OUT_0, 279 E_DMD_DVBC_CCI_FREQN_OUT_1, 280 E_DMD_DVBC_RF_GAIN_MIN, 281 E_DMD_DVBC_RF_GAIN_MAX, 282 E_DMD_DVBC_IF_GAIN_MIN, 283 E_DMD_DVBC_IF_GAIN_MAX, 284 E_DMD_DVBC_NO_SIGNAL_NUM_TH, 285 E_DMD_DVBC_NO_SIGNAL_GAIN_TH_L, 286 E_DMD_DVBC_NO_SIGNAL_GAIN_TH_H, 287 E_DMD_DVBC_NO_SIGNAL_ERR_TH_L, 288 E_DMD_DVBC_NO_SIGNAL_ERR_TH_H, //0x50 289 E_DMD_DVBC_TUNER_NUM, 290 E_DMD_DVBC_UNCRT_PKT_NUM_7_0, 291 E_DMD_DVBC_UNCRT_PKT_NUM_8_15, 292 E_DMD_DVBC_STATE, 293 E_DMD_DVBC_ILL_LOCK, 294 E_DMD_DVBC_DAGC1_REF, 295 E_DMD_DVBC_DAGC2_REF, 296 E_DMD_DVBC_EQ_KP3_16QAM, 297 E_DMD_DVBC_EQ_KP3_32QAM, 298 E_DMD_DVBC_EQ_KP3_64QAM, 299 E_DMD_DVBC_EQ_KP3_128QAM, 300 E_DMD_DVBC_EQ_KP3_256QAM, 301 E_DMD_DVBC_EQ_KP4_16QAM, 302 E_DMD_DVBC_EQ_KP4_32QAM, 303 E_DMD_DVBC_EQ_KP4_64QAM, 304 E_DMD_DVBC_EQ_KP4_128QAM, //0x60 305 E_DMD_DVBC_EQ_KP4_256QAM, 306 E_DMD_DVBC_SNR100_L, 307 E_DMD_DVBC_SNR100_H, 308 E_DMD_DVBC_CFO10_L, 309 E_DMD_DVBC_CFO10_H, 310 E_DMD_DVBC_TR_LOCK, 311 E_DMD_DVBC_CR_LOCK, 312 E_DMD_DVBC_EQ_DMA1_LOCK, 313 E_DMD_DVBC_EQ_DMA_LOCK, 314 E_DMD_DVBC_EQ_DD1_LOCK, 315 E_DMD_DVBC_EQ_DD_LOCK, 316 E_DMD_DVBC_FEC_LOCK, //0x6C 317 E_DMD_DVBC_CHIP_VERSION, 318 } DVBC_Param_2; 319 320 typedef enum 321 { 322 // Operation Mode Settings 323 e_opmode_rfagc_en, //0 324 e_opmode_humdet_en, 325 e_opmode_dcr_en, 326 e_opmode_iqb_en, 327 e_opmode_auto_iq, 328 e_opmode_auto_rfmax, 329 e_opmode_auto_aci, 330 e_opmode_auto_scan, 331 e_opmode_auto_scan_sym_rate, 332 e_opmode_auto_scan_qam, 333 e_opmode_atv_detector_en, 334 e_opmode_no_sig_if_gain_th_l, 335 e_opmode_no_sig_if_gain_th_h, 336 e_opmode_no_sig_if_err_th_l, 337 e_opmode_no_sig_if_err_th_h, 338 e_opmode_rsv_0x0F, //15 339 // Config Params 340 e_config_rssi, 341 e_config_zif, 342 e_config_freq, 343 e_config_fc_l, 344 e_config_fc_h,//20 345 e_config_fs_l, 346 e_config_fs_h, 347 e_config_bw_l, 348 e_config_bw_h, 349 e_config_bw1_l,//25 350 e_config_bw1_h, 351 e_config_bw2_l, 352 e_config_bw2_h, 353 e_config_bw3_l, 354 e_config_bw3_h,//30 355 e_config_rsv_0x1F, 356 e_config_rfmax, 357 e_config_qam, 358 e_config_iq_swap, 359 e_config_cci, 360 e_config_ts_serial, 361 e_config_ts_clk_rate, 362 e_config_ts_out_inv, 363 e_config_ts_data_swap, 364 e_config_lif, 365 e_config_fif_l, 366 e_config_fif_h, 367 e_config_tuner_sawless, 368 DVBC_PARAM_LEN, 369 } DVBC_Param; 370 371 #ifdef UFO_DEMOD_DVBC_SUPPORT_DMD_INT 372 /// For demod init 373 typedef enum 374 { 375 E_DMD_DVBC_INT_UNKNOWN=0, 376 E_DMD_DVBC_INT_LOCK, 377 E_DMD_DVBC_INT_UNLOCK 378 } DMD_DVBC_INT_TYPE; 379 380 typedef void (*fpIntCallBack)(MS_U8 u8arg); 381 #endif 382 383 typedef struct 384 { 385 // tuner parameter 386 MS_U8 u8SarChannel; 387 DMD_RFAGC_SSI *pTuner_RfagcSsi; 388 MS_U16 u16Tuner_RfagcSsi_Size; 389 DMD_IFAGC_SSI *pTuner_IfagcSsi_LoRef; 390 MS_U16 u16Tuner_IfagcSsi_LoRef_Size; 391 DMD_IFAGC_SSI *pTuner_IfagcSsi_HiRef; 392 MS_U16 u16Tuner_IfagcSsi_HiRef_Size; 393 DMD_IFAGC_ERR *pTuner_IfagcErr_LoRef; 394 MS_U16 u16Tuner_IfagcErr_LoRef_Size; 395 DMD_IFAGC_ERR *pTuner_IfagcErr_HiRef; 396 MS_U16 u16Tuner_IfagcErr_HiRef_Size; 397 DMD_SQI_CN_NORDIGP1 *pSqiCnNordigP1; 398 MS_U16 u16SqiCnNordigP1_Size; 399 400 // register init 401 MS_U8 *u8DMD_DVBC_DSPRegInitExt; // TODO use system variable type 402 MS_U8 u8DMD_DVBC_DSPRegInitSize; 403 MS_U8 *u8DMD_DVBC_InitExt; // TODO use system variable type 404 405 //Interrupt callback 406 //fpIntCallBack fpCB; 407 } DMD_DVBC_InitData; 408 409 typedef enum 410 { 411 E_DMD_DVBC_FAIL=0, 412 E_DMD_DVBC_OK=1 413 } DMD_DVBC_Result; 414 415 416 typedef struct 417 { 418 MS_U16 u16Version; 419 MS_U16 u16SymbolRate; 420 DMD_DVBC_MODULATION_TYPE eQamMode; 421 MS_U32 u32IFFreq; 422 MS_BOOL bSpecInv; 423 MS_BOOL bSerialTS; 424 MS_U8 u8SarValue; 425 MS_U32 u32ChkScanTimeStart; 426 DMD_DVBC_LOCK_STATUS eLockStatus; 427 MS_U16 u16Strength; 428 MS_U16 u16Quality; 429 MS_U32 u32Intp; // 430 MS_U32 u32FcFs; // 431 MS_U8 u8Qam; // 432 MS_U16 u16SymbolRateHal; // 433 } DMD_DVBC_Info; 434 435 //typedef void(*P_DMD_ISR_Proc)(MS_U8 u8DMDID); 436 437 438 //------------------------------------------------------------------------------------------------- 439 // Function and Variable 440 //------------------------------------------------------------------------------------------------- 441 //////////////////////////////////////////////////////////////////////////////// 442 /// MDrv_DMD_DVBT_Init 443 //////////////////////////////////////////////////////////////////////////////// 444 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_Init(DMD_DVBC_InitData *pDMD_DVBC_InitData, MS_U32 u32InitDataLen); 445 //////////////////////////////////////////////////////////////////////////////// 446 /// Should be called when exit VD input source 447 //////////////////////////////////////////////////////////////////////////////// 448 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_Exit(void); 449 //////////////////////////////////////////////////////////////////////////////// 450 /// Get Initial Data 451 /// @ingroup DVBC_BASIC 452 /// @param pDMD_DVBC_InitData \b IN: DVBC initial parameters 453 /// @return TRUE : succeed 454 /// @return FALSE : fail 455 //------------------------------------------------------------------------------------------------- 456 extern DLL_PUBLIC MS_U32 SYMBOL_WEAK MDrv_DMD_DVBC_GetConfig(DMD_DVBC_InitData *pDMD_DVBC_InitData); 457 //////////////////////////////////////////////////////////////////////////////// 458 //------------------------------------------------------------------------------ 459 /// Set detailed level of DVBT driver debug message 460 /// u8DbgLevel : debug level for Parallel Flash driver\n 461 /// AVD_DBGLV_NONE, ///< disable all the debug message\n 462 /// AVD_DBGLV_INFO, ///< information\n 463 /// AVD_DBGLV_NOTICE, ///< normal but significant condition\n 464 /// AVD_DBGLV_WARNING, ///< warning conditions\n 465 /// AVD_DBGLV_ERR, ///< error conditions\n 466 /// AVD_DBGLV_CRIT, ///< critical conditions\n 467 /// AVD_DBGLV_ALERT, ///< action must be taken immediately\n 468 /// AVD_DBGLV_EMERG, ///< system is unusable\n 469 /// AVD_DBGLV_DEBUG, ///< debug-level messages\n 470 /// @return TRUE : succeed 471 /// @return FALSE : failed to set the debug level 472 //------------------------------------------------------------------------------ 473 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_SetDbgLevel(DMD_DVBC_DbgLv u8DbgLevel); 474 //------------------------------------------------------------------------------------------------- 475 /// Get the information of DVBT driver\n 476 /// @return the pointer to the driver information 477 //------------------------------------------------------------------------------------------------- 478 extern DLL_PUBLIC const DMD_DVBC_Info* MDrv_DMD_DVBC_GetInfo(void); 479 //------------------------------------------------------------------------------------------------- 480 /// Get DVBT driver version 481 /// when get ok, return the pointer to the driver version 482 //------------------------------------------------------------------------------------------------- 483 484 /////////////////////////////////////////////////////////////////////////////////// 485 ///To get/set the DSP parameter table from demod MCU 486 //u16Addr :the address of the demod MCU DSP parameter table 487 ////////////////////////////////////////////////////////////////////////////////// 488 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_GetDSPReg(MS_U16 u16Addr, MS_U8 *pu8Data); 489 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_SetDSPReg(MS_U16 u16Addr, MS_U8 pu8Data); 490 491 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_GetLibVer(const MSIF_Version **ppVersion); 492 //////////////////////////////////////////////////////////////////////////////// 493 /// To get DVBT's register value, only for special purpose.\n 494 /// u16Addr : the address of DVBT's register\n 495 /// return the value of AFEC's register\n 496 //////////////////////////////////////////////////////////////////////////////// 497 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data); 498 //////////////////////////////////////////////////////////////////////////////// 499 /// To set DVBT's register value, only for special purpose.\n 500 /// u16Addr : the address of DVBT's register\n 501 /// u8Value : the value to be set\n 502 //////////////////////////////////////////////////////////////////////////////// 503 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_GetFWVer(MS_U16 *ver); 504 //////////////////////////////////////////////////////////////////////////////// 505 /// Get DVBC FW version 506 /// u16Addr : the address of DVBC's register\n 507 //////////////////////////////////////////////////////////////////////////////// 508 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_SetReg(MS_U16 u16Addr, MS_U8 u8Data); 509 //////////////////////////////////////////////////////////////////////////////// 510 /// MDrv_DMD_DVBT_SetSerialControl 511 //////////////////////////////////////////////////////////////////////////////// 512 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_SetSerialControl(MS_BOOL bEnable); 513 //////////////////////////////////////////////////////////////////////////////// 514 /// MDrv_DMD_DVBT_SetConfig 515 //////////////////////////////////////////////////////////////////////////////// 516 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_SetConfig(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS); 517 //////////////////////////////////////////////////////////////////////////////// 518 /// MDrv_DMD_DVBT_SetConfig_symbol_rate_list 519 //////////////////////////////////////////////////////////////////////////////// 520 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_SetConfig_symbol_rate_list(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num); 521 //////////////////////////////////////////////////////////////////////////////// 522 /// MDrv_DMD_DVBT_SetActive 523 //////////////////////////////////////////////////////////////////////////////// 524 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_SetActive(MS_BOOL bEnable); 525 //////////////////////////////////////////////////////////////////////////////// 526 /// MDrv_DMD_DVBT_Get_Lock 527 //////////////////////////////////////////////////////////////////////////////// 528 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType, DMD_DVBC_LOCK_STATUS *eLockStatus); 529 //////////////////////////////////////////////////////////////////////////////// 530 /// MDrv_DMD_DVBC_GetLockWithRFPower 531 //////////////////////////////////////////////////////////////////////////////// 532 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_GetLockWithRFPower(DMD_DVBC_GETLOCK_TYPE eType, DMD_DVBC_LOCK_STATUS *eLockStatus, float fCurrRFPowerDbm, float fNoChannelRFPowerDbm); 533 //////////////////////////////////////////////////////////////////////////////// 534 /// MDrv_DMD_DVBT_GetSignalStrength 535 //////////////////////////////////////////////////////////////////////////////// 536 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_GetSignalStrength(MS_U16 *u16Strength); 537 //////////////////////////////////////////////////////////////////////////////// 538 /// MDrv_DMD_DVBC_GetSignalStrengthWithRFPower 539 //////////////////////////////////////////////////////////////////////////////// 540 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_GetSignalStrengthWithRFPower(MS_U16 *u16Strength, float fRFPowerDbm); 541 //////////////////////////////////////////////////////////////////////////////// 542 /// MDrv_DMD_DVBC_GetSignalQuality 543 //////////////////////////////////////////////////////////////////////////////// 544 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_GetSignalQuality(MS_U16 *u16Quality); 545 //////////////////////////////////////////////////////////////////////////////// 546 /// MDrv_DMD_DVBC_GetSignalQualityWithRFPower 547 //////////////////////////////////////////////////////////////////////////////// 548 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_GetSignalQualityWithRFPower(MS_U16 *u16Quality, float fRFPowerDbm); 549 //////////////////////////////////////////////////////////////////////////////// 550 /// MDrv_DMD_DVBC_GetSNR 551 //////////////////////////////////////////////////////////////////////////////// 552 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_GetSNR(float *fSNR); 553 //////////////////////////////////////////////////////////////////////////////// 554 /// MDrv_DMD_DVBC_GetPostViterbiBer 555 //////////////////////////////////////////////////////////////////////////////// 556 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_GetPostViterbiBer(float *ber); 557 //////////////////////////////////////////////////////////////////////////////// 558 /// MDrv_DMD_DVBC_GetPacketErr 559 //////////////////////////////////////////////////////////////////////////////// 560 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_GetPacketErr(MS_U16 *pktErr); 561 //////////////////////////////////////////////////////////////////////////////// 562 /// MDrv_DMD_DVBT_GetCellID 563 //////////////////////////////////////////////////////////////////////////////// 564 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_GetCellID(MS_U16 *u16CellID); 565 //////////////////////////////////////////////////////////////////////////////// 566 /// MDrv_DMD_DVBC_GetStatus 567 //////////////////////////////////////////////////////////////////////////////// 568 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_GetStatus(DMD_DVBC_MODULATION_TYPE *pQAMMode, MS_U16 *u16SymbolRate, float *pFreqOff); 569 570 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_ActiveDmdSwitch(MS_U8 demod_no); 571 572 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_Dual_Individual_Init(DMD_DVBC_InitData *pDMD_DVBC_InitData, MS_U32 u32InitDataLen); 573 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBC_Dual_Public_Init(MS_U8 u8AGC_Tristate_Ctrl,MS_U8 u8Sar_Channel); 574 575 extern DLL_PUBLIC MS_U32 MDrv_DMD_DVBC_SetPowerState(EN_POWER_MODE u16PowerState); 576 577 #ifdef UFO_DEMOD_DVBC_SUPPORT_DMD_INT 578 MS_BOOL MDrv_DMD_DVBC_Reg_INT_CB(fpIntCallBack fpCBReg); 579 #endif 580 581 #ifdef UFO_DEMOD_DVBC_GET_AGC_INFO 582 MS_BOOL MDrv_DMD_DVBC_GetAGCInfo(MS_U8 u8dbg_mode, MS_U16 *pu16Data); 583 #endif 584 585 586 587 #ifdef __cplusplus 588 } 589 #endif 590 591 592 #endif // _DRV_DVBC_H_ 593 594