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Searched refs:EQE2_REG_BASE (Results 1 – 13 of 13) sorted by relevance

/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_DVBC.c137 #define EQE2_REG_BASE 0x2d00UL macro
1953 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data); in INTERN_DVBC_GetSNR()
1956 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data); in INTERN_DVBC_GetSNR()
2289 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, &reg); in INTERN_DVBC_Get_FreqOffset()
2291 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, &reg); in INTERN_DVBC_Get_FreqOffset()
2293 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, &reg); in INTERN_DVBC_Get_FreqOffset()
2295 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, &reg); in INTERN_DVBC_Get_FreqOffset()
2364 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0xC4, &u8Data); in INTERN_DVBC_GetCurrentModulationType()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_DVBC.c134 #define EQE2_REG_BASE 0x2d00 macro
1691 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data); in INTERN_DVBC_GetSNR()
1693 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data); in INTERN_DVBC_GetSNR()
2008 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, &reg); in INTERN_DVBC_Get_FreqOffset()
2010 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, &reg); in INTERN_DVBC_Get_FreqOffset()
2012 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, &reg); in INTERN_DVBC_Get_FreqOffset()
2014 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, &reg); in INTERN_DVBC_Get_FreqOffset()
2081 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0xC4, &u8Data); in INTERN_DVBC_GetCurrentModulationType()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBC.c137 #define EQE2_REG_BASE 0x9c00UL // P2 = 1, 0x11c00 -> 0x1c00 macro
1547 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data); in INTERN_DVBC_GetSNR()
1550 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data); in INTERN_DVBC_GetSNR()
1882 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, &reg); in INTERN_DVBC_Get_FreqOffset()
1884 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, &reg); in INTERN_DVBC_Get_FreqOffset()
1886 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, &reg); in INTERN_DVBC_Get_FreqOffset()
1888 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBC.c137 #define EQE2_REG_BASE 0x9c00UL // P2 = 1, 0x11c00 -> 0x1c00 macro
1547 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data); in INTERN_DVBC_GetSNR()
1550 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data); in INTERN_DVBC_GetSNR()
1882 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, &reg); in INTERN_DVBC_Get_FreqOffset()
1884 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, &reg); in INTERN_DVBC_Get_FreqOffset()
1886 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, &reg); in INTERN_DVBC_Get_FreqOffset()
1888 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBC.c137 #define EQE2_REG_BASE 0x9c00UL // P2 = 1, 0x11c00 -> 0x1c00 macro
1597 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data); in INTERN_DVBC_GetSNR()
1600 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data); in INTERN_DVBC_GetSNR()
1932 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, &reg); in INTERN_DVBC_Get_FreqOffset()
1934 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, &reg); in INTERN_DVBC_Get_FreqOffset()
1936 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, &reg); in INTERN_DVBC_Get_FreqOffset()
1938 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBC.c137 #define EQE2_REG_BASE 0x9c00UL // P2 = 1, 0x11c00 -> 0x1c00 macro
1547 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data); in INTERN_DVBC_GetSNR()
1550 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data); in INTERN_DVBC_GetSNR()
1882 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, &reg); in INTERN_DVBC_Get_FreqOffset()
1884 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, &reg); in INTERN_DVBC_Get_FreqOffset()
1886 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, &reg); in INTERN_DVBC_Get_FreqOffset()
1888 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBC.c137 #define EQE2_REG_BASE 0x9c00UL // P2 = 1, 0x11c00 -> 0x1c00 macro
1597 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data); in INTERN_DVBC_GetSNR()
1600 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data); in INTERN_DVBC_GetSNR()
1932 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, &reg); in INTERN_DVBC_Get_FreqOffset()
1934 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, &reg); in INTERN_DVBC_Get_FreqOffset()
1936 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, &reg); in INTERN_DVBC_Get_FreqOffset()
1938 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBC.c137 #define EQE2_REG_BASE 0x9c00UL // P2 = 1, 0x11c00 -> 0x1c00 macro
1547 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data); in INTERN_DVBC_GetSNR()
1550 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data); in INTERN_DVBC_GetSNR()
1882 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, &reg); in INTERN_DVBC_Get_FreqOffset()
1884 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, &reg); in INTERN_DVBC_Get_FreqOffset()
1886 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, &reg); in INTERN_DVBC_Get_FreqOffset()
1888 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBC.c137 #define EQE2_REG_BASE 0x9c00UL // P2 = 1, 0x11c00 -> 0x1c00 macro
1547 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data); in INTERN_DVBC_GetSNR()
1550 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data); in INTERN_DVBC_GetSNR()
1882 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, &reg); in INTERN_DVBC_Get_FreqOffset()
1884 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, &reg); in INTERN_DVBC_Get_FreqOffset()
1886 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, &reg); in INTERN_DVBC_Get_FreqOffset()
1888 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBC.c135 #define EQE2_REG_BASE 0x9c00UL macro
1493 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data); in INTERN_DVBC_GetSNR()
1495 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data); in INTERN_DVBC_GetSNR()
1810 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, &reg); in INTERN_DVBC_Get_FreqOffset()
1812 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, &reg); in INTERN_DVBC_Get_FreqOffset()
1814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, &reg); in INTERN_DVBC_Get_FreqOffset()
1816 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBC.c134 #define EQE2_REG_BASE 0x9c00UL macro
1497 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data); in INTERN_DVBC_GetSNR()
1499 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data); in INTERN_DVBC_GetSNR()
1814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, &reg); in INTERN_DVBC_Get_FreqOffset()
1816 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, &reg); in INTERN_DVBC_Get_FreqOffset()
1818 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, &reg); in INTERN_DVBC_Get_FreqOffset()
1820 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_DVBC.c1951 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data); in INTERN_DVBC_GetSNR()
1953 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data); in INTERN_DVBC_GetSNR()
2285 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, &reg); in INTERN_DVBC_Get_FreqOffset()
2287 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, &reg); in INTERN_DVBC_Get_FreqOffset()
2289 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, &reg); in INTERN_DVBC_Get_FreqOffset()
2291 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBC.c140 #define EQE2_REG_BASE 0x9c00UL // P2 = 1, 0x11c00 -> 0x1c00 macro
3341 …status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75+BANK_BASE_OFFSET*hal_demod_swtich_statu… in INTERN_DVBC_Get_FreqOffset()
3343 …status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74+BANK_BASE_OFFSET*hal_demod_swtich_statu… in INTERN_DVBC_Get_FreqOffset()
3345 …status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73+BANK_BASE_OFFSET*hal_demod_swtich_statu… in INTERN_DVBC_Get_FreqOffset()
3347 …status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72+BANK_BASE_OFFSET*hal_demod_swtich_statu… in INTERN_DVBC_Get_FreqOffset()