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Searched refs:CHANNEL0_IF5_CONFIG2 (Results 1 – 10 of 10) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tso/
H A DhalTSO.c441 reg16 = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
893 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
920 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1234 reg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_ChIf_Cfg()
1281 pReg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h365 REG16_TSO CHANNEL0_IF5_CONFIG2; //16 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tso/
H A DhalTSO.c441 reg16 = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
893 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
920 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1234 reg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_ChIf_Cfg()
1281 pReg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h365 REG16_TSO CHANNEL0_IF5_CONFIG2; //16 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tso/
H A DhalTSO.c441 reg16 = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
896 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
923 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1266 reg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_ChIf_Cfg()
1313 pReg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h365 REG16_TSO CHANNEL0_IF5_CONFIG2; //16 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tso/
H A DhalTSO.c439 reg16 = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
902 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
929 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1272 reg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_ChIf_Cfg()
1319 pReg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h376 REG16_TSO CHANNEL0_IF5_CONFIG2; //16 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tso/
H A DhalTSO.c442 reg16 = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
905 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
932 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1275 reg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_ChIf_Cfg()
1322 pReg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h380 REG16_TSO CHANNEL0_IF5_CONFIG2; //16 member