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Searched refs:CHANNEL0_IF4_CONFIG2 (Results 1 – 10 of 10) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tso/
H A DhalTSO.c437 reg16 = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
890 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
917 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1231 reg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_ChIf_Cfg()
1278 pReg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h333 REG16_TSO CHANNEL0_IF4_CONFIG2; //12 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tso/
H A DhalTSO.c437 reg16 = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
890 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
917 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1231 reg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_ChIf_Cfg()
1278 pReg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h333 REG16_TSO CHANNEL0_IF4_CONFIG2; //12 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tso/
H A DhalTSO.c437 reg16 = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
893 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
920 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1263 reg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_ChIf_Cfg()
1310 pReg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h333 REG16_TSO CHANNEL0_IF4_CONFIG2; //12 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tso/
H A DhalTSO.c435 reg16 = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
899 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
926 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1269 reg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_ChIf_Cfg()
1316 pReg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h342 REG16_TSO CHANNEL0_IF4_CONFIG2; //12 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tso/
H A DhalTSO.c438 reg16 = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
902 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
929 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1272 reg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_ChIf_Cfg()
1319 pReg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h346 REG16_TSO CHANNEL0_IF4_CONFIG2; //12 member