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Searched refs:CHANNEL0_IF3_CONFIG2 (Results 1 – 10 of 10) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tso/
H A DhalTSO.c433 reg16 = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
887 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
914 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1228 reg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_ChIf_Cfg()
1275 pReg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h301 REG16_TSO CHANNEL0_IF3_CONFIG2; //0e member
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tso/
H A DhalTSO.c433 reg16 = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
887 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
914 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1228 reg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_ChIf_Cfg()
1275 pReg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h301 REG16_TSO CHANNEL0_IF3_CONFIG2; //0e member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tso/
H A DhalTSO.c433 reg16 = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
890 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
917 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1260 reg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_ChIf_Cfg()
1307 pReg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h301 REG16_TSO CHANNEL0_IF3_CONFIG2; //0e member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tso/
H A DhalTSO.c431 reg16 = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
896 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
923 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1266 reg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_ChIf_Cfg()
1313 pReg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h308 REG16_TSO CHANNEL0_IF3_CONFIG2; //0e member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tso/
H A DhalTSO.c434 reg16 = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
899 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
926 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1269 reg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_ChIf_Cfg()
1316 pReg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h312 REG16_TSO CHANNEL0_IF3_CONFIG2; //0e member