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Searched refs:CHANNEL0_IF1_CONFIG2 (Results 1 – 10 of 10) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tso/
H A DhalTSO.c425 reg16 = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
881 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
908 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1222 reg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_ChIf_Cfg()
1269 pReg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h235 REG16_TSO CHANNEL0_IF1_CONFIG2; //06 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tso/
H A DhalTSO.c425 reg16 = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
881 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
908 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1222 reg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_ChIf_Cfg()
1269 pReg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h235 REG16_TSO CHANNEL0_IF1_CONFIG2; //06 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tso/
H A DhalTSO.c425 reg16 = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
884 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
911 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1254 reg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_ChIf_Cfg()
1301 pReg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h235 REG16_TSO CHANNEL0_IF1_CONFIG2; //06 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tso/
H A DhalTSO.c423 reg16 = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
890 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
917 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1260 reg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_ChIf_Cfg()
1307 pReg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h237 REG16_TSO CHANNEL0_IF1_CONFIG2; //06 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tso/
H A DhalTSO.c426 reg16 = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
893 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
920 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1263 reg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_ChIf_Cfg()
1310 pReg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h241 REG16_TSO CHANNEL0_IF1_CONFIG2; //06 member