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Searched refs:reg_base (Results 1 – 21 of 21) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkenc/jpege/
H A Dhal_jpege_vpu720.c376 JpegeVpu720BaseReg *reg_base = &regs->reg_base; in hal_jpege_vpu720_gen_regs() local
411 reg_base->reg001_enc_strt.lkt_num = 0; in hal_jpege_vpu720_gen_regs()
412 reg_base->reg001_enc_strt.vepu_cmd = ctx->enc_mode; in hal_jpege_vpu720_gen_regs()
415 reg_base->reg004_int_en.fenc_done_en = 1; in hal_jpege_vpu720_gen_regs()
416 reg_base->reg004_int_en.lkt_node_done_en = 1; in hal_jpege_vpu720_gen_regs()
417 reg_base->reg004_int_en.sclr_done_en = 1; in hal_jpege_vpu720_gen_regs()
418 reg_base->reg004_int_en.vslc_done_en = 1; in hal_jpege_vpu720_gen_regs()
419 reg_base->reg004_int_en.vbsb_oflw_en = 1; in hal_jpege_vpu720_gen_regs()
420 reg_base->reg004_int_en.vbsb_sct_en = 1; in hal_jpege_vpu720_gen_regs()
421 reg_base->reg004_int_en.fenc_err_en = 1; in hal_jpege_vpu720_gen_regs()
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H A Dhal_jpege_vepu540c.c144 jpeg_vepu540c_base *reg_base = &regs->reg_base; in hal_jpege_v540c_gen_regs() local
155 cfg.jpeg_reg_base = &reg_base->jpegReg; in hal_jpege_v540c_gen_regs()
201 reg_base->reg0192_enc_pic.enc_stnd = 2; // disable h264 or hevc in hal_jpege_v540c_gen_regs()
272 cfg.reg = &hw_regs->reg_base; in hal_jpege_v540c_start()
H A Dhal_jpege_vepu511.c308 Vepu511JpegRoiRegion *reg_regions = &regs->reg_base.jpegReg.roi_regions[0]; in hal_jpege_vepu511_set_roi()
360 JpegVepu511Base *reg_base = &regs->reg_base; in hal_jpege_vepu511_gen_regs() local
372 cfg.jpeg_reg_base = &reg_base->jpegReg; in hal_jpege_vepu511_gen_regs()
425 reg_base->common.enc_pic.enc_stnd = 2; // disable h264 or hevc in hal_jpege_vepu511_gen_regs()
429 reg_base->common.enc_pic.jpeg_slen_fifo = 0; in hal_jpege_vepu511_gen_regs()
501 cfg.reg = &hw_regs->reg_base; in hal_jpege_vepu511_start()
H A Dhal_jpege_vepu511_reg.h373 JpegVepu511Base reg_base; member
H A Dhal_jpege_vpu720_reg.h550 JpegeVpu720BaseReg reg_base; member
H A Dhal_jpege_vepu540c_reg.h848 jpeg_vepu540c_base reg_base; member
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu540c.c469 regs->reg_base.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu540c_prep()
470 regs->reg_base.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu540c_prep()
471 regs->reg_base.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu540c_prep()
472 regs->reg_base.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu540c_prep()
476 regs->reg_base.src_fmt.src_cfmt = hw_fmt; in setup_vepu540c_prep()
477 regs->reg_base.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu540c_prep()
478 regs->reg_base.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu540c_prep()
479 regs->reg_base.src_fmt.out_fmt = (fmt == MPP_FMT_YUV400) ? 0 : 1; in setup_vepu540c_prep()
492 regs->reg_base.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu540c_prep()
493 regs->reg_base.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu540c_prep()
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H A Dhal_h264e_vepu580.c370 p->osd_cfg.reg_base = &p->regs_sets->reg_osd; in hal_h264e_vepu580_init()
603 ctx->osd_cfg.reg_base = &ctx->regs_set->reg_osd; in hal_h264e_vepu580_get_task()
718 regs->reg_base.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu580_prep()
719 regs->reg_base.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu580_prep()
720 regs->reg_base.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu580_prep()
721 regs->reg_base.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu580_prep()
725 regs->reg_base.src_fmt.src_cfmt = hw_fmt; in setup_vepu580_prep()
726 regs->reg_base.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu580_prep()
727 regs->reg_base.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu580_prep()
728 regs->reg_base.src_fmt.out_fmt = (fmt == MPP_FMT_YUV400) ? 0 : 1; in setup_vepu580_prep()
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H A Dhal_h264e_vepu580_tune.c152 regs->reg_base.iprd_csts.vthd_y = 0; in vepu580_h264e_tune_reg_patch()
153 regs->reg_base.iprd_csts.vthd_c = 0; in vepu580_h264e_tune_reg_patch()
155 regs->reg_base.rdo_cfg.atf_intra_e = 0; in vepu580_h264e_tune_reg_patch()
H A Dhal_h264e_vepu540c_reg.h1067 Vepu540cBaseCfg reg_base; member
H A Dhal_h264e_vepu580_reg.h2935 Vepu580BaseCfg reg_base; member
H A Dhal_h264e_vepu541.c193 p->osd_cfg.reg_base = &p->regs_set; in hal_h264e_vepu541_init()
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu540c.c710 hevc_vepu540c_base *reg_base = &regs->reg_base; in vepu540c_h265_set_rc_regs() local
724 reg_base->reg0192_enc_pic.pic_qp = rc_cfg->quality_target; in vepu540c_h265_set_rc_regs()
725 reg_base->reg0240_synt_sli1.sli_qp = rc_cfg->quality_target; in vepu540c_h265_set_rc_regs()
727 reg_base->reg213_rc_qp.rc_max_qp = rc_cfg->quality_target; in vepu540c_h265_set_rc_regs()
728 reg_base->reg213_rc_qp.rc_min_qp = rc_cfg->quality_target; in vepu540c_h265_set_rc_regs()
737 reg_base->reg0192_enc_pic.pic_qp = rc_cfg->quality_target; in vepu540c_h265_set_rc_regs()
738 reg_base->reg0240_synt_sli1.sli_qp = rc_cfg->quality_target; in vepu540c_h265_set_rc_regs()
739 reg_base->reg212_rc_cfg.rc_en = 1; in vepu540c_h265_set_rc_regs()
740 reg_base->reg212_rc_cfg.aq_en = 1; in vepu540c_h265_set_rc_regs()
741 reg_base->reg212_rc_cfg.aq_mode = 0; in vepu540c_h265_set_rc_regs()
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H A Dhal_h265e_vepu580.c1542 frm_cfg->osd_cfg.reg_base = &frm_cfg->regs_set[0]->reg_osd_cfg; in hal_h265e_v580_init()
1823 regs->reg_base.reg0220_me_rnge.cme_srch_v = 1; in setup_intra_refresh()
1825 regs->reg_base.reg0220_me_rnge.cme_srch_h = 1; in setup_intra_refresh()
1827 regs->reg_base.reg0192_enc_pic.roi_en = 1; in setup_intra_refresh()
1828 regs->reg_base.reg0178_roi_addr = roi_base_cfg_buf_fd; in setup_intra_refresh()
1894 hevc_vepu580_base *reg_base = &regs->reg_base; in vepu580_h265_set_rc_regs() local
1909 reg_base->reg0192_enc_pic.pic_qp = rc_cfg->quality_target; in vepu580_h265_set_rc_regs()
1910 reg_base->reg0240_synt_sli1.sli_qp = rc_cfg->quality_target; in vepu580_h265_set_rc_regs()
1912 reg_base->reg213_rc_qp.rc_max_qp = rc_cfg->quality_target; in vepu580_h265_set_rc_regs()
1913 reg_base->reg213_rc_qp.rc_min_qp = rc_cfg->quality_target; in vepu580_h265_set_rc_regs()
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H A Dhal_h265e_vepu540c_reg.h1071 hevc_vepu540c_base reg_base; member
H A Dhal_h265e_vepu580_reg.h3255 hevc_vepu580_base reg_base; member
H A Dhal_h265e_vepu541.c629 ctx->osd_cfg.reg_base = ctx->regs; in hal_h265e_v541_init()
/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu5xx_common.h70 void *reg_base; member
H A Dvepu580_common.c13 Vepu580OsdReg *regs = (Vepu580OsdReg *)cfg->reg_base; in vepu580_set_osd()
H A Dvepu541_common.c248 Vepu541OsdReg *regs = (Vepu541OsdReg *)(cfg->reg_base + (size_t)VEPU541_OSD_CFG_OFFSET); in vepu541_set_osd()
447 Vepu540OsdReg *regs = (Vepu540OsdReg *)(cfg->reg_base + (size_t)VEPU540_OSD_CFG_OFFSET); in vepu540_set_osd()
H A Dvepu511_common.h2980 void *reg_base; member