1542         frm_cfg->osd_cfg.reg_base = &frm_cfg->regs_set[0]->reg_osd_cfg;  in hal_h265e_v580_init()
1823         regs->reg_base.reg0220_me_rnge.cme_srch_v = 1;  in setup_intra_refresh()
1825         regs->reg_base.reg0220_me_rnge.cme_srch_h = 1;  in setup_intra_refresh()
1827     regs->reg_base.reg0192_enc_pic.roi_en = 1;  in setup_intra_refresh()
1828     regs->reg_base.reg0178_roi_addr = roi_base_cfg_buf_fd;  in setup_intra_refresh()
1894     hevc_vepu580_base *reg_base = &regs->reg_base;  in vepu580_h265_set_rc_regs()  local
1909         reg_base->reg0192_enc_pic.pic_qp    = rc_cfg->quality_target;  in vepu580_h265_set_rc_regs()
1910         reg_base->reg0240_synt_sli1.sli_qp  = rc_cfg->quality_target;  in vepu580_h265_set_rc_regs()
1912         reg_base->reg213_rc_qp.rc_max_qp   = rc_cfg->quality_target;  in vepu580_h265_set_rc_regs()
1913         reg_base->reg213_rc_qp.rc_min_qp   = rc_cfg->quality_target;  in vepu580_h265_set_rc_regs()
1922         reg_base->reg0192_enc_pic.pic_qp    = rc_cfg->quality_target;  in vepu580_h265_set_rc_regs()
1923         reg_base->reg0240_synt_sli1.sli_qp  = rc_cfg->quality_target;  in vepu580_h265_set_rc_regs()
1924         reg_base->reg212_rc_cfg.rc_en      = 1;  in vepu580_h265_set_rc_regs()
1925         reg_base->reg212_rc_cfg.aq_en  = 1;  in vepu580_h265_set_rc_regs()
1926         reg_base->reg212_rc_cfg.aq_mode    = 1;  in vepu580_h265_set_rc_regs()
1927         reg_base->reg212_rc_cfg.rc_ctu_num = mb_wd64;  in vepu580_h265_set_rc_regs()
1928         reg_base->reg213_rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ?  in vepu580_h265_set_rc_regs()
1930         reg_base->reg213_rc_qp.rc_max_qp   = rc_cfg->quality_max;  in vepu580_h265_set_rc_regs()
1931         reg_base->reg213_rc_qp.rc_min_qp   = rc_cfg->quality_min;  in vepu580_h265_set_rc_regs()
1932         reg_base->reg214_rc_tgt.ctu_ebit  = ctu_target_bits_mul_16;  in vepu580_h265_set_rc_regs()
1955             reg_base->reg213_rc_qp.rc_qp_range = 0;  in vepu580_h265_set_rc_regs()
1984     hevc_vepu580_base        *reg_base = &regs->reg_base;  in vepu580_h265_set_pp_regs()  local
1989     reg_base->reg0198_src_fmt.src_cfmt = fmt->format;  in vepu580_h265_set_pp_regs()
1990     reg_base->reg0198_src_fmt.alpha_swap = fmt->alpha_swap;  in vepu580_h265_set_pp_regs()
1991     reg_base->reg0198_src_fmt.rbuv_swap = fmt->rbuv_swap;  in vepu580_h265_set_pp_regs()
1992     reg_base->reg0198_src_fmt.out_fmt = (prep_cfg->format == MPP_FMT_YUV400) ? 0 : 1;  in vepu580_h265_set_pp_regs()
1993     reg_base->reg0203_src_proc.src_mirr = prep_cfg->mirroring > 0;  in vepu580_h265_set_pp_regs()
1994     reg_base->reg0203_src_proc.src_rot = prep_cfg->rotation;  in vepu580_h265_set_pp_regs()
1997         reg_base->reg0198_src_fmt.src_range = 1;  in vepu580_h265_set_pp_regs()
1999         reg_base->reg0198_src_fmt.src_range = (prep_cfg->range == MPP_FRAME_RANGE_JPEG) ? 1 : 0;  in vepu580_h265_set_pp_regs()
2034     if (reg_base->reg0198_src_fmt.src_cfmt < VEPU5xx_FMT_ARGB1555) {  in vepu580_h265_set_pp_regs()
2039         reg_base->reg0199_src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff;  in vepu580_h265_set_pp_regs()
2040         reg_base->reg0199_src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff;  in vepu580_h265_set_pp_regs()
2041         reg_base->reg0199_src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff;  in vepu580_h265_set_pp_regs()
2043         reg_base->reg0200_src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff;  in vepu580_h265_set_pp_regs()
2044         reg_base->reg0200_src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff;  in vepu580_h265_set_pp_regs()
2045         reg_base->reg0200_src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff;  in vepu580_h265_set_pp_regs()
2047         reg_base->reg0201_src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff;  in vepu580_h265_set_pp_regs()
2048         reg_base->reg0201_src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff;  in vepu580_h265_set_pp_regs()
2049         reg_base->reg0201_src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff;  in vepu580_h265_set_pp_regs()
2051         reg_base->reg0202_src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset;  in vepu580_h265_set_pp_regs()
2052         reg_base->reg0202_src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset;  in vepu580_h265_set_pp_regs()
2053         reg_base->reg0202_src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset;  in vepu580_h265_set_pp_regs()
2058     reg_base->reg0205_src_strd0.src_strd0  = stridey;  in vepu580_h265_set_pp_regs()
2059     reg_base->reg0206_src_strd1.src_strd1  = stridec;  in vepu580_h265_set_pp_regs()
2188     cfg.reg = &hw_regs->reg_base;  in hal_h265e_v580_send_regs()
2199         regs = (RK_U32*)(&hw_regs->reg_base);  in hal_h265e_v580_send_regs()
2291     hevc_vepu580_base *reg_base = &regs->reg_base;  in setup_vepu580_dual_core()  local
2301     reg_base->reg0193_dual_core.dchs_txid = ctx->curr_idx;  in setup_vepu580_dual_core()
2302     reg_base->reg0193_dual_core.dchs_rxid = ctx->prev_idx;  in setup_vepu580_dual_core()
2303     reg_base->reg0193_dual_core.dchs_txe = 1;  in setup_vepu580_dual_core()
2304     reg_base->reg0193_dual_core.dchs_rxe = dchs_rxe;  in setup_vepu580_dual_core()
2305     reg_base->reg0193_dual_core.dchs_ofst = dchs_ofst;  in setup_vepu580_dual_core()
2448     hevc_vepu580_base *regs = &frm->regs_set[0]->reg_base;  in vepu580_h265_set_hw_address()
2540     hevc_vepu580_base *reg_base = &regs->reg_base;  in vepu580_h265e_save_pass1_patch()  local
2554     reg_base->reg0192_enc_pic.cur_frm_ref = 1;  in vepu580_h265e_save_pass1_patch()
2555     reg_base->reg0163_rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1);  in vepu580_h265e_save_pass1_patch()
2556     reg_base->reg0164_rfpw_b_addr = reg_base->reg0163_rfpw_h_addr;  in vepu580_h265e_save_pass1_patch()
2557     reg_base->reg0192_enc_pic.rec_fbc_dis = 1;  in vepu580_h265e_save_pass1_patch()
2560         reg_base->reg0238_synt_pps.lpf_fltr_acrs_til = 0;  in vepu580_h265e_save_pass1_patch()
2565     regs->reg_base.reg0216_sli_splt.sli_splt = 0;  in vepu580_h265e_save_pass1_patch()
2566     regs->reg_base.reg0192_enc_pic.slen_fifo = 0;  in vepu580_h265e_save_pass1_patch()
2575     hevc_vepu580_base *reg_base = &regs->reg_base;  in vepu580_h265e_use_pass1_patch()  local
2583     reg_base->reg0198_src_fmt.src_cfmt = VEPU5xx_FMT_YUV420SP;  in vepu580_h265e_use_pass1_patch()
2584     reg_base->reg0198_src_fmt.alpha_swap = 0;  in vepu580_h265e_use_pass1_patch()
2585     reg_base->reg0198_src_fmt.rbuv_swap = 0;  in vepu580_h265e_use_pass1_patch()
2586     reg_base->reg0198_src_fmt.out_fmt = 1;  in vepu580_h265e_use_pass1_patch()
2587     reg_base->reg0203_src_proc.afbcd_en = 0;  in vepu580_h265e_use_pass1_patch()
2588     reg_base->reg0205_src_strd0.src_strd0 = hor_stride;  in vepu580_h265e_use_pass1_patch()
2589     reg_base->reg0206_src_strd1.src_strd1 = hor_stride;  in vepu580_h265e_use_pass1_patch()
2590     reg_base->reg0203_src_proc.src_mirr = 0;  in vepu580_h265e_use_pass1_patch()
2591     reg_base->reg0203_src_proc.src_rot = 0;  in vepu580_h265e_use_pass1_patch()
2592     reg_base->reg0204_pic_ofst.pic_ofst_x = 0;  in vepu580_h265e_use_pass1_patch()
2593     reg_base->reg0204_pic_ofst.pic_ofst_y = 0;  in vepu580_h265e_use_pass1_patch()
2594     reg_base->reg0160_adr_src0 = mpp_buffer_get_fd(ctx->buf_pass1);  in vepu580_h265e_use_pass1_patch()
2595     reg_base->reg0161_adr_src1 = reg_base->reg0160_adr_src0;  in vepu580_h265e_use_pass1_patch()
2596     reg_base->reg0162_adr_src2 = reg_base->reg0160_adr_src0;  in vepu580_h265e_use_pass1_patch()
2619         regs->reg_base.reg0216_sli_splt.sli_splt = 0;  in vepu580_setup_split()
2620         regs->reg_base.reg0216_sli_splt.sli_splt_mode = 0;  in vepu580_setup_split()
2621         regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0;  in vepu580_setup_split()
2622         regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 0;  in vepu580_setup_split()
2623         regs->reg_base.reg0216_sli_splt.sli_flsh = 0;  in vepu580_setup_split()
2624         regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = 0;  in vepu580_setup_split()
2626         regs->reg_base.reg0217_sli_byte.sli_splt_byte = 0;  in vepu580_setup_split()
2627         regs->reg_base.reg0192_enc_pic.slen_fifo = 0;  in vepu580_setup_split()
2630         regs->reg_base.reg0216_sli_splt.sli_splt = 1;  in vepu580_setup_split()
2631         regs->reg_base.reg0216_sli_splt.sli_splt_mode = 0;  in vepu580_setup_split()
2632         regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0;  in vepu580_setup_split()
2633         regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 500;  in vepu580_setup_split()
2634         regs->reg_base.reg0216_sli_splt.sli_flsh = 1;  in vepu580_setup_split()
2635         regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = 0;  in vepu580_setup_split()
2637         regs->reg_base.reg0217_sli_byte.sli_splt_byte = cfg->split_arg;  in vepu580_setup_split()
2638         regs->reg_base.reg0192_enc_pic.slen_fifo = cfg->split_out ? 1 : 0;  in vepu580_setup_split()
2639         regs->reg_ctl.reg0008_int_en.slc_done_en = regs->reg_base.reg0192_enc_pic.slen_fifo;  in vepu580_setup_split()
2651         regs->reg_base.reg0216_sli_splt.sli_splt = 1;  in vepu580_setup_split()
2652         regs->reg_base.reg0216_sli_splt.sli_splt_mode = 1;  in vepu580_setup_split()
2653         regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0;  in vepu580_setup_split()
2654         regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 500;  in vepu580_setup_split()
2655         regs->reg_base.reg0216_sli_splt.sli_flsh = 1;  in vepu580_setup_split()
2656         regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1;  in vepu580_setup_split()
2658         regs->reg_base.reg0217_sli_byte.sli_splt_byte = 0;  in vepu580_setup_split()
2659         regs->reg_base.reg0192_enc_pic.slen_fifo = cfg->split_out ? 1 : 0;  in vepu580_setup_split()
2662             (regs->reg_base.reg0192_enc_pic.slen_fifo && (slice_num > VEPU580_SLICE_FIFO_LEN)))  in vepu580_setup_split()
2686     hevc_vepu580_base        *reg_base = &regs->reg_base;  in hal_h265e_v580_gen_regs()  local
2742     reg_base->reg0196_enc_rsl.pic_wd8_m1    = pic_width_align8 / 8 - 1;  in hal_h265e_v580_gen_regs()
2743     reg_base->reg0197_src_fill.pic_wfill    = (syn->pp.pic_width & 0x7)  in hal_h265e_v580_gen_regs()
2745     reg_base->reg0196_enc_rsl.pic_hd8_m1    = pic_height_align8 / 8 - 1;  in hal_h265e_v580_gen_regs()
2746     reg_base->reg0197_src_fill.pic_hfill    = (syn->pp.pic_height & 0x7)  in hal_h265e_v580_gen_regs()
2749     reg_base->reg0192_enc_pic.enc_stnd      = 1; //H265  in hal_h265e_v580_gen_regs()
2750 …reg_base->reg0192_enc_pic.cur_frm_ref   = !syn->sp.non_reference_flag; //current frame will be ref…  in hal_h265e_v580_gen_regs()
2751     reg_base->reg0192_enc_pic.bs_scp        = 1;  in hal_h265e_v580_gen_regs()
2752     reg_base->reg0192_enc_pic.log2_ctu_num  = ceil(log2((double)pic_wd64 * pic_h64));  in hal_h265e_v580_gen_regs()
2754     reg_base->reg0203_src_proc.src_mirr = 0;  in hal_h265e_v580_gen_regs()
2755     reg_base->reg0203_src_proc.src_rot  = 0;  in hal_h265e_v580_gen_regs()
2756     reg_base->reg0203_src_proc.txa_en   = 1;  in hal_h265e_v580_gen_regs()
2757     reg_base->reg0203_src_proc.afbcd_en = (MPP_FRAME_FMT_IS_FBC(syn->pp.mpp_format)) ? 1 : 0;  in hal_h265e_v580_gen_regs()
2762     vepu580_h265_set_me_regs(ctx, syn, reg_base);  in hal_h265e_v580_gen_regs()
2764     reg_base->reg0232_rdo_cfg.chrm_spcl   = 1;  in hal_h265e_v580_gen_regs()
2765     reg_base->reg0232_rdo_cfg.cu_inter_e    = 0x06db;  in hal_h265e_v580_gen_regs()
2766     reg_base->reg0232_rdo_cfg.cu_intra_e    = 0xf;  in hal_h265e_v580_gen_regs()
2769         reg_base->reg0232_rdo_cfg.ltm_col   = 0;  in hal_h265e_v580_gen_regs()
2770         reg_base->reg0232_rdo_cfg.ltm_idx0l0 = 1;  in hal_h265e_v580_gen_regs()
2772         reg_base->reg0232_rdo_cfg.ltm_col   = 0;  in hal_h265e_v580_gen_regs()
2773         reg_base->reg0232_rdo_cfg.ltm_idx0l0 = 0;  in hal_h265e_v580_gen_regs()
2776     reg_base->reg0232_rdo_cfg.ccwa_e = 1;  in hal_h265e_v580_gen_regs()
2777     reg_base->reg0232_rdo_cfg.scl_lst_sel = syn->pp.scaling_list_enabled_flag;  in hal_h265e_v580_gen_regs()
2778     reg_base->reg0236_synt_nal.nal_unit_type = h265e_get_nal_type(&syn->sp, ctx->frame_type);  in hal_h265e_v580_gen_regs()
2783     vepu580_h265_set_slice_regs(syn, reg_base);  in hal_h265e_v580_gen_regs()
2784     vepu580_h265_set_ref_regs(syn, reg_base);  in hal_h265e_v580_gen_regs()
2788     vepu580_h265_set_roi_regs(ctx, reg_base);  in hal_h265e_v580_gen_regs()
2886         hevc_vepu580_base *reg_base = NULL;  in hal_h265e_v580_start()  local
2898         reg_base = &hw_regs->reg_base;  in hal_h265e_v580_start()
2903         vepu580_h265_set_me_ram(syn, reg_base, k, tile_start_x);  in hal_h265e_v580_start()
2908             hal_h265e_v580_set_uniform_tile(reg_base, syn, k, tile_start_x);  in hal_h265e_v580_start()
2913             reg_base->reg0176_lpfw_addr  = mpp_buffer_get_fd(frm->hw_tile_buf[k]);  in hal_h265e_v580_start()
2914             reg_base->reg0177_lpfr_addr  = mpp_buffer_get_fd(frm->hw_tile_buf[k - 1]);  in hal_h265e_v580_start()
2920                 reg_base->reg0173_bsbb_addr = mpp_buffer_get_fd(enc_task->output);  in hal_h265e_v580_start()
2925                 reg_base->reg0172_bsbt_addr = mpp_buffer_get_fd(frm->hw_tile_stream[k - 1]);  in hal_h265e_v580_start()
2927                 reg_base->reg0173_bsbb_addr = reg_base->reg0172_bsbt_addr;  in hal_h265e_v580_start()
2928                 reg_base->reg0174_bsbr_addr = reg_base->reg0172_bsbt_addr;  in hal_h265e_v580_start()
2929                 reg_base->reg0175_adr_bsbs  = reg_base->reg0172_bsbt_addr;  in hal_h265e_v580_start()
3211         hevc_vepu580_base *reg_base = &regs->reg_base;  in hal_h265e_v580_wait()  local
3212         RK_U32 type = reg_base->reg0236_synt_nal.nal_unit_type;  in hal_h265e_v580_wait()
3275         hevc_vepu580_base *reg_base = &regs->reg_base;  in hal_h265e_v580_wait()  local
3276         RK_U32 type = reg_base->reg0236_synt_nal.nal_unit_type;  in hal_h265e_v580_wait()