Lines Matching refs:reg_base
469 regs->reg_base.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu540c_prep()
470 regs->reg_base.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu540c_prep()
471 regs->reg_base.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu540c_prep()
472 regs->reg_base.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu540c_prep()
476 regs->reg_base.src_fmt.src_cfmt = hw_fmt; in setup_vepu540c_prep()
477 regs->reg_base.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu540c_prep()
478 regs->reg_base.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu540c_prep()
479 regs->reg_base.src_fmt.out_fmt = (fmt == MPP_FMT_YUV400) ? 0 : 1; in setup_vepu540c_prep()
492 regs->reg_base.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu540c_prep()
493 regs->reg_base.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu540c_prep()
494 regs->reg_base.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu540c_prep()
496 regs->reg_base.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu540c_prep()
497 regs->reg_base.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu540c_prep()
498 regs->reg_base.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu540c_prep()
500 regs->reg_base.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; in setup_vepu540c_prep()
501 regs->reg_base.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in setup_vepu540c_prep()
502 regs->reg_base.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in setup_vepu540c_prep()
504 regs->reg_base.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in setup_vepu540c_prep()
505 regs->reg_base.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu540c_prep()
506 regs->reg_base.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset; in setup_vepu540c_prep()
510 regs->reg_base.src_udfy.csc_wgt_b2y = cfg.weight[0]; in setup_vepu540c_prep()
511 regs->reg_base.src_udfy.csc_wgt_g2y = cfg.weight[1]; in setup_vepu540c_prep()
512 regs->reg_base.src_udfy.csc_wgt_r2y = cfg.weight[2]; in setup_vepu540c_prep()
514 regs->reg_base.src_udfu.csc_wgt_b2u = cfg.weight[3]; in setup_vepu540c_prep()
515 regs->reg_base.src_udfu.csc_wgt_g2u = cfg.weight[4]; in setup_vepu540c_prep()
516 regs->reg_base.src_udfu.csc_wgt_r2u = cfg.weight[5]; in setup_vepu540c_prep()
518 regs->reg_base.src_udfv.csc_wgt_b2v = cfg.weight[6]; in setup_vepu540c_prep()
519 regs->reg_base.src_udfv.csc_wgt_g2v = cfg.weight[7]; in setup_vepu540c_prep()
520 regs->reg_base.src_udfv.csc_wgt_r2v = cfg.weight[8]; in setup_vepu540c_prep()
522 regs->reg_base.src_udfo.csc_ofst_y = cfg.offset[0]; in setup_vepu540c_prep()
523 regs->reg_base.src_udfo.csc_ofst_u = cfg.offset[1]; in setup_vepu540c_prep()
524 regs->reg_base.src_udfo.csc_ofst_v = cfg.offset[2]; in setup_vepu540c_prep()
527 regs->reg_base.src_strd0.src_strd0 = y_stride; in setup_vepu540c_prep()
528 regs->reg_base.src_strd1.src_strd1 = c_stride; in setup_vepu540c_prep()
530 regs->reg_base.src_proc.src_mirr = prep->mirroring > 0; in setup_vepu540c_prep()
531 regs->reg_base.src_proc.src_rot = prep->rotation; in setup_vepu540c_prep()
534 regs->reg_base.sli_cfg.mv_v_lmt_thd = 0; in setup_vepu540c_prep()
535 regs->reg_base.sli_cfg.mv_v_lmt_en = 0; in setup_vepu540c_prep()
537 regs->reg_base.pic_ofst.pic_ofst_y = 0; in setup_vepu540c_prep()
538 regs->reg_base.pic_ofst.pic_ofst_x = 0; in setup_vepu540c_prep()
550 regs->reg_base.enc_pic.enc_stnd = 0; in setup_vepu540c_codec()
551 regs->reg_base.enc_pic.cur_frm_ref = slice->nal_reference_idc > 0; in setup_vepu540c_codec()
552 regs->reg_base.enc_pic.bs_scp = 1; in setup_vepu540c_codec()
554 regs->reg_base.synt_nal.nal_ref_idc = slice->nal_reference_idc; in setup_vepu540c_codec()
555 regs->reg_base.synt_nal.nal_unit_type = slice->nalu_type; in setup_vepu540c_codec()
557 regs->reg_base.synt_sps.max_fnum = sps->log2_max_frame_num_minus4; in setup_vepu540c_codec()
558 regs->reg_base.synt_sps.drct_8x8 = sps->direct8x8_inference; in setup_vepu540c_codec()
559 regs->reg_base.synt_sps.mpoc_lm4 = sps->log2_max_poc_lsb_minus4; in setup_vepu540c_codec()
561 regs->reg_base.synt_pps.etpy_mode = pps->entropy_coding_mode; in setup_vepu540c_codec()
562 regs->reg_base.synt_pps.trns_8x8 = pps->transform_8x8_mode; in setup_vepu540c_codec()
563 regs->reg_base.synt_pps.csip_flag = pps->constrained_intra_pred; in setup_vepu540c_codec()
564 regs->reg_base.synt_pps.num_ref0_idx = pps->num_ref_idx_l0_default_active - 1; in setup_vepu540c_codec()
565 regs->reg_base.synt_pps.num_ref1_idx = pps->num_ref_idx_l1_default_active - 1; in setup_vepu540c_codec()
566 regs->reg_base.synt_pps.pic_init_qp = pps->pic_init_qp; in setup_vepu540c_codec()
567 regs->reg_base.synt_pps.cb_ofst = pps->chroma_qp_index_offset; in setup_vepu540c_codec()
568 regs->reg_base.synt_pps.cr_ofst = pps->second_chroma_qp_index_offset; in setup_vepu540c_codec()
569 regs->reg_base.synt_pps.dbf_cp_flg = pps->deblocking_filter_control; in setup_vepu540c_codec()
571 regs->reg_base.synt_sli0.sli_type = (slice->slice_type == H264_I_SLICE) ? (2) : (0); in setup_vepu540c_codec()
572 regs->reg_base.synt_sli0.pps_id = slice->pic_parameter_set_id; in setup_vepu540c_codec()
573 regs->reg_base.synt_sli0.drct_smvp = 0; in setup_vepu540c_codec()
574 regs->reg_base.synt_sli0.num_ref_ovrd = slice->num_ref_idx_override; in setup_vepu540c_codec()
575 regs->reg_base.synt_sli0.cbc_init_idc = slice->cabac_init_idc; in setup_vepu540c_codec()
576 regs->reg_base.synt_sli0.frm_num = slice->frame_num; in setup_vepu540c_codec()
578 …regs->reg_base.synt_sli1.idr_pid = (slice->slice_type == H264_I_SLICE) ? slice->idr_pic_id … in setup_vepu540c_codec()
579 regs->reg_base.synt_sli1.poc_lsb = slice->pic_order_cnt_lsb; in setup_vepu540c_codec()
582 regs->reg_base.synt_sli2.dis_dblk_idc = slice->disable_deblocking_filter_idc; in setup_vepu540c_codec()
583 regs->reg_base.synt_sli2.sli_alph_ofst = slice->slice_alpha_c0_offset_div2; in setup_vepu540c_codec()
591 regs->reg_base.synt_sli2.ref_list0_rodr = 1; in setup_vepu540c_codec()
592 regs->reg_base.synt_sli2.rodr_pic_idx = rplmo.modification_of_pic_nums_idc; in setup_vepu540c_codec()
597 regs->reg_base.synt_sli2.rodr_pic_num = rplmo.abs_diff_pic_num_minus1; in setup_vepu540c_codec()
600 regs->reg_base.synt_sli2.rodr_pic_num = rplmo.long_term_pic_idx; in setup_vepu540c_codec()
609 regs->reg_base.synt_sli2.ref_list0_rodr = 0; in setup_vepu540c_codec()
610 regs->reg_base.synt_sli2.rodr_pic_idx = 0; in setup_vepu540c_codec()
611 regs->reg_base.synt_sli2.rodr_pic_num = 0; in setup_vepu540c_codec()
616 regs->reg_base.synt_refm0.nopp_flg = 0; in setup_vepu540c_codec()
617 regs->reg_base.synt_refm0.ltrf_flg = 0; in setup_vepu540c_codec()
618 regs->reg_base.synt_refm0.arpm_flg = 0; in setup_vepu540c_codec()
619 regs->reg_base.synt_refm0.mmco4_pre = 0; in setup_vepu540c_codec()
620 regs->reg_base.synt_refm0.mmco_type0 = 0; in setup_vepu540c_codec()
621 regs->reg_base.synt_refm0.mmco_parm0 = 0; in setup_vepu540c_codec()
622 regs->reg_base.synt_refm0.mmco_type1 = 0; in setup_vepu540c_codec()
623 regs->reg_base.synt_refm1.mmco_parm1 = 0; in setup_vepu540c_codec()
624 regs->reg_base.synt_refm0.mmco_type2 = 0; in setup_vepu540c_codec()
625 regs->reg_base.synt_refm1.mmco_parm2 = 0; in setup_vepu540c_codec()
626 regs->reg_base.synt_refm2.long_term_frame_idx0 = 0; in setup_vepu540c_codec()
627 regs->reg_base.synt_refm2.long_term_frame_idx1 = 0; in setup_vepu540c_codec()
628 regs->reg_base.synt_refm2.long_term_frame_idx2 = 0; in setup_vepu540c_codec()
634 regs->reg_base.synt_refm0.nopp_flg = slice->no_output_of_prior_pics; in setup_vepu540c_codec()
635 regs->reg_base.synt_refm0.ltrf_flg = slice->long_term_reference_flag; in setup_vepu540c_codec()
640 regs->reg_base.synt_refm0.arpm_flg = 1; in setup_vepu540c_codec()
675 regs->reg_base.synt_refm0.mmco_type0 = type; in setup_vepu540c_codec()
676 regs->reg_base.synt_refm0.mmco_parm0 = param_0; in setup_vepu540c_codec()
677 regs->reg_base.synt_refm2.long_term_frame_idx0 = param_1; in setup_vepu540c_codec()
711 regs->reg_base.synt_refm0.mmco_type1 = type; in setup_vepu540c_codec()
712 regs->reg_base.synt_refm1.mmco_parm1 = param_0; in setup_vepu540c_codec()
713 regs->reg_base.synt_refm2.long_term_frame_idx1 = param_1; in setup_vepu540c_codec()
747 regs->reg_base.synt_refm0.mmco_type2 = type; in setup_vepu540c_codec()
748 regs->reg_base.synt_refm1.mmco_parm2 = param_0; in setup_vepu540c_codec()
749 regs->reg_base.synt_refm2.long_term_frame_idx2 = param_1; in setup_vepu540c_codec()
768 regs->reg_base.rdo_cfg.rect_size = (sps->profile_idc == H264_PROFILE_BASELINE && in setup_vepu540c_rdo_pred()
770 regs->reg_base.rdo_cfg.vlc_lmt = (sps->profile_idc < H264_PROFILE_MAIN) && in setup_vepu540c_rdo_pred()
772 regs->reg_base.rdo_cfg.chrm_spcl = 1; in setup_vepu540c_rdo_pred()
773 regs->reg_base.rdo_cfg.ccwa_e = 1; in setup_vepu540c_rdo_pred()
774 regs->reg_base.rdo_cfg.scl_lst_sel = pps->pic_scaling_matrix_present; in setup_vepu540c_rdo_pred()
775 regs->reg_base.rdo_cfg.atf_e = 1; in setup_vepu540c_rdo_pred()
776 regs->reg_base.rdo_cfg.atr_e = 1; in setup_vepu540c_rdo_pred()
777 regs->reg_base.rdo_cfg.intra_cost_e = 1; in setup_vepu540c_rdo_pred()
778 regs->reg_base.iprd_csts.rdo_mark_mode = 0x100; in setup_vepu540c_rdo_pred()
932 regs->reg_base.enc_pic.pic_qp = rc_info->quality_target; in setup_vepu540c_rc_base()
933 regs->reg_base.rc_qp.rc_max_qp = rc_info->quality_target; in setup_vepu540c_rc_base()
934 regs->reg_base.rc_qp.rc_min_qp = rc_info->quality_target; in setup_vepu540c_rc_base()
946 regs->reg_base.enc_pic.pic_qp = qp_target; in setup_vepu540c_rc_base()
948 regs->reg_base.rc_cfg.rc_en = 1; in setup_vepu540c_rc_base()
949 regs->reg_base.rc_cfg.aq_en = 1; in setup_vepu540c_rc_base()
950 regs->reg_base.rc_cfg.aq_mode = 0; in setup_vepu540c_rc_base()
951 regs->reg_base.rc_cfg.rc_ctu_num = mb_w; in setup_vepu540c_rc_base()
953 regs->reg_base.rc_qp.rc_qp_range = (slice->slice_type == H264_I_SLICE) ? in setup_vepu540c_rc_base()
955 regs->reg_base.rc_qp.rc_max_qp = qp_max; in setup_vepu540c_rc_base()
956 regs->reg_base.rc_qp.rc_min_qp = qp_min; in setup_vepu540c_rc_base()
958 regs->reg_base.rc_tgt.ctu_ebit = mb_target_bits_mul_16; in setup_vepu540c_rc_base()
1001 regs->reg_base.adr_src0 = fd_in; in setup_vepu540c_io_buf()
1002 regs->reg_base.adr_src1 = fd_in; in setup_vepu540c_io_buf()
1003 regs->reg_base.adr_src2 = fd_in; in setup_vepu540c_io_buf()
1005 regs->reg_base.bsbt_addr = fd_out; in setup_vepu540c_io_buf()
1006 regs->reg_base.bsbb_addr = fd_out; in setup_vepu540c_io_buf()
1007 regs->reg_base.adr_bsbs = fd_out; in setup_vepu540c_io_buf()
1008 regs->reg_base.bsbr_addr = fd_out; in setup_vepu540c_io_buf()
1012 regs->reg_base.rfpt_h_addr = 0xffffffff; in setup_vepu540c_io_buf()
1013 regs->reg_base.rfpb_h_addr = 0; in setup_vepu540c_io_buf()
1014 regs->reg_base.rfpt_b_addr = 0xffffffff; in setup_vepu540c_io_buf()
1015 regs->reg_base.adr_rfpb_b = 0; in setup_vepu540c_io_buf()
1083 regs->reg_base.rfpw_h_addr = fd; in setup_vepu540c_recn_refr()
1084 regs->reg_base.rfpw_b_addr = fd; in setup_vepu540c_recn_refr()
1085 regs->reg_base.dspw_addr = mpp_buffer_get_fd(buf_thumb); in setup_vepu540c_recn_refr()
1097 regs->reg_base.rfpr_h_addr = fd; in setup_vepu540c_recn_refr()
1098 regs->reg_base.rfpr_b_addr = fd; in setup_vepu540c_recn_refr()
1099 regs->reg_base.dspr_addr = mpp_buffer_get_fd(buf_thumb); in setup_vepu540c_recn_refr()
1111 regs->reg_base.sli_splt.sli_splt = 0; in setup_vepu540c_split()
1112 regs->reg_base.sli_splt.sli_splt_mode = 0; in setup_vepu540c_split()
1113 regs->reg_base.sli_splt.sli_splt_cpst = 0; in setup_vepu540c_split()
1114 regs->reg_base.sli_splt.sli_max_num_m1 = 0; in setup_vepu540c_split()
1115 regs->reg_base.sli_splt.sli_flsh = 0; in setup_vepu540c_split()
1116 regs->reg_base.sli_cnum.sli_splt_cnum_m1 = 0; in setup_vepu540c_split()
1118 regs->reg_base.sli_byte.sli_splt_byte = 0; in setup_vepu540c_split()
1119 regs->reg_base.enc_pic.slen_fifo = 0; in setup_vepu540c_split()
1122 regs->reg_base.sli_splt.sli_splt = 1; in setup_vepu540c_split()
1123 regs->reg_base.sli_splt.sli_splt_mode = 0; in setup_vepu540c_split()
1124 regs->reg_base.sli_splt.sli_splt_cpst = 0; in setup_vepu540c_split()
1125 regs->reg_base.sli_splt.sli_max_num_m1 = 500; in setup_vepu540c_split()
1126 regs->reg_base.sli_splt.sli_flsh = 1; in setup_vepu540c_split()
1127 regs->reg_base.sli_cnum.sli_splt_cnum_m1 = 0; in setup_vepu540c_split()
1129 regs->reg_base.sli_byte.sli_splt_byte = cfg->split.split_arg; in setup_vepu540c_split()
1130 regs->reg_base.enc_pic.slen_fifo = 0; in setup_vepu540c_split()
1131 regs->reg_base.enc_pic.slen_fifo = cfg->split.split_out ? 1 : 0; in setup_vepu540c_split()
1132 regs->reg_ctl.int_en.vslc_done_en = regs->reg_base.enc_pic.slen_fifo; in setup_vepu540c_split()
1139 regs->reg_base.sli_splt.sli_splt = 1; in setup_vepu540c_split()
1140 regs->reg_base.sli_splt.sli_splt_mode = 1; in setup_vepu540c_split()
1141 regs->reg_base.sli_splt.sli_splt_cpst = 0; in setup_vepu540c_split()
1142 regs->reg_base.sli_splt.sli_max_num_m1 = 500; in setup_vepu540c_split()
1143 regs->reg_base.sli_splt.sli_flsh = 1; in setup_vepu540c_split()
1144 regs->reg_base.sli_cnum.sli_splt_cnum_m1 = cfg->split.split_arg - 1; in setup_vepu540c_split()
1146 regs->reg_base.sli_byte.sli_splt_byte = 0; in setup_vepu540c_split()
1147 regs->reg_base.enc_pic.slen_fifo = cfg->split.split_out ? 1 : 0; in setup_vepu540c_split()
1149 (regs->reg_base.enc_pic.slen_fifo && (slice_num > VEPU540C_SLICE_FIFO_LEN))) in setup_vepu540c_split()
1162 Vepu540cBaseCfg *base_regs = ®s->reg_base; in calc_cime_parameter()
1250 regs->reg_base.me_rnge.cime_srch_dwnh = 15; in setup_vepu540c_me()
1251 regs->reg_base.me_rnge.cime_srch_uph = 14; in setup_vepu540c_me()
1252 regs->reg_base.me_rnge.cime_srch_rgtw = 12; in setup_vepu540c_me()
1253 regs->reg_base.me_rnge.cime_srch_lftw = 12; in setup_vepu540c_me()
1254 regs->reg_base.me_cfg.rme_srch_h = 3; in setup_vepu540c_me()
1255 regs->reg_base.me_cfg.rme_srch_v = 3; in setup_vepu540c_me()
1257 regs->reg_base.me_cfg.srgn_max_num = 72; in setup_vepu540c_me()
1258 regs->reg_base.me_cfg.cime_dist_thre = 1024; in setup_vepu540c_me()
1259 regs->reg_base.me_cfg.rme_dis = 0; in setup_vepu540c_me()
1260 regs->reg_base.me_cfg.fme_dis = 0; in setup_vepu540c_me()
1261 regs->reg_base.me_rnge.dlt_frm_num = 0x0; in setup_vepu540c_me()
1448 regs->reg_base.ebuft_addr = fd; in setup_vepu540c_ext_line_buf()
1449 regs->reg_base.ebufb_addr = fd; in setup_vepu540c_ext_line_buf()
1453 regs->reg_base.ebuft_addr = 0; in setup_vepu540c_ext_line_buf()
1454 regs->reg_base.ebufb_addr = 0; in setup_vepu540c_ext_line_buf()
1490 regs->reg_base.meiw_addr = task->md_info ? mpp_buffer_get_fd(task->md_info) : 0; in hal_h264e_vepu540c_gen_regs()
1492 regs->reg_base.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame); in hal_h264e_vepu540c_gen_regs()
1493 regs->reg_base.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame); in hal_h264e_vepu540c_gen_regs()
1543 wr_cfg.reg = &ctx->regs_set->reg_base; in hal_h264e_vepu540c_start()
1544 wr_cfg.size = sizeof(ctx->regs_set->reg_base); in hal_h264e_vepu540c_start()