Lines Matching refs:reg_base
710 hevc_vepu540c_base *reg_base = ®s->reg_base; in vepu540c_h265_set_rc_regs() local
724 reg_base->reg0192_enc_pic.pic_qp = rc_cfg->quality_target; in vepu540c_h265_set_rc_regs()
725 reg_base->reg0240_synt_sli1.sli_qp = rc_cfg->quality_target; in vepu540c_h265_set_rc_regs()
727 reg_base->reg213_rc_qp.rc_max_qp = rc_cfg->quality_target; in vepu540c_h265_set_rc_regs()
728 reg_base->reg213_rc_qp.rc_min_qp = rc_cfg->quality_target; in vepu540c_h265_set_rc_regs()
737 reg_base->reg0192_enc_pic.pic_qp = rc_cfg->quality_target; in vepu540c_h265_set_rc_regs()
738 reg_base->reg0240_synt_sli1.sli_qp = rc_cfg->quality_target; in vepu540c_h265_set_rc_regs()
739 reg_base->reg212_rc_cfg.rc_en = 1; in vepu540c_h265_set_rc_regs()
740 reg_base->reg212_rc_cfg.aq_en = 1; in vepu540c_h265_set_rc_regs()
741 reg_base->reg212_rc_cfg.aq_mode = 0; in vepu540c_h265_set_rc_regs()
742 reg_base->reg212_rc_cfg.rc_ctu_num = mb_wd32; in vepu540c_h265_set_rc_regs()
743 reg_base->reg213_rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ? in vepu540c_h265_set_rc_regs()
745 reg_base->reg213_rc_qp.rc_max_qp = rc_cfg->quality_max; in vepu540c_h265_set_rc_regs()
746 reg_base->reg213_rc_qp.rc_min_qp = rc_cfg->quality_min; in vepu540c_h265_set_rc_regs()
747 reg_base->reg214_rc_tgt.ctu_ebit = ctu_target_bits_mul_16; in vepu540c_h265_set_rc_regs()
794 hevc_vepu540c_base *reg_base = ®s->reg_base; in vepu540c_h265_set_pp_regs() local
799 reg_base->reg0198_src_fmt.src_cfmt = fmt->format; in vepu540c_h265_set_pp_regs()
800 reg_base->reg0198_src_fmt.alpha_swap = fmt->alpha_swap; in vepu540c_h265_set_pp_regs()
801 reg_base->reg0198_src_fmt.rbuv_swap = fmt->rbuv_swap; in vepu540c_h265_set_pp_regs()
803 reg_base->reg0198_src_fmt.out_fmt = (prep_cfg->format == MPP_FMT_YUV400) ? 0 : 1; in vepu540c_h265_set_pp_regs()
804 reg_base->reg0203_src_proc.src_mirr = prep_cfg->mirroring > 0; in vepu540c_h265_set_pp_regs()
805 reg_base->reg0203_src_proc.src_rot = prep_cfg->rotation; in vepu540c_h265_set_pp_regs()
810 if (reg_base->reg0198_src_fmt.src_cfmt == VEPU5xx_FMT_BGRA8888 ) in vepu540c_h265_set_pp_regs()
812 else if (reg_base->reg0198_src_fmt.src_cfmt == VEPU5xx_FMT_BGR888 ) in vepu540c_h265_set_pp_regs()
814 else if (reg_base->reg0198_src_fmt.src_cfmt == VEPU5xx_FMT_BGR565 || in vepu540c_h265_set_pp_regs()
815 reg_base->reg0198_src_fmt.src_cfmt == VEPU5xx_FMT_YUYV422 || in vepu540c_h265_set_pp_regs()
816 reg_base->reg0198_src_fmt.src_cfmt == VEPU5xx_FMT_UYVY422) in vepu540c_h265_set_pp_regs()
820 stridec = (reg_base->reg0198_src_fmt.src_cfmt == VEPU5xx_FMT_YUV422SP || in vepu540c_h265_set_pp_regs()
821 reg_base->reg0198_src_fmt.src_cfmt == VEPU5xx_FMT_YUV420SP) ? in vepu540c_h265_set_pp_regs()
824 if (reg_base->reg0198_src_fmt.src_cfmt < VEPU5xx_FMT_ARGB1555) { in vepu540c_h265_set_pp_regs()
829 reg_base->reg0199_src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in vepu540c_h265_set_pp_regs()
830 reg_base->reg0199_src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in vepu540c_h265_set_pp_regs()
831 reg_base->reg0199_src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in vepu540c_h265_set_pp_regs()
833 reg_base->reg0200_src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in vepu540c_h265_set_pp_regs()
834 reg_base->reg0200_src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in vepu540c_h265_set_pp_regs()
835 reg_base->reg0200_src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in vepu540c_h265_set_pp_regs()
837 reg_base->reg0201_src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in vepu540c_h265_set_pp_regs()
838 reg_base->reg0201_src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in vepu540c_h265_set_pp_regs()
839 reg_base->reg0201_src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; in vepu540c_h265_set_pp_regs()
841 reg_base->reg0202_src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in vepu540c_h265_set_pp_regs()
842 reg_base->reg0202_src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in vepu540c_h265_set_pp_regs()
843 reg_base->reg0202_src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset; in vepu540c_h265_set_pp_regs()
848 reg_base->reg0205_src_strd0.src_strd0 = stridey; in vepu540c_h265_set_pp_regs()
849 reg_base->reg0206_src_strd1.src_strd1 = stridec; in vepu540c_h265_set_pp_regs()
1121 regs->reg_base.reg0179_adr_ebufb = fd; in setup_vepu540c_ext_line_buf()
1122 regs->reg_base.reg0178_adr_ebuft = fd; in setup_vepu540c_ext_line_buf()
1125 regs->reg_base.reg0179_adr_ebufb = 0; in setup_vepu540c_ext_line_buf()
1126 regs->reg_base.reg0178_adr_ebuft = 0; in setup_vepu540c_ext_line_buf()
1138 regs->reg_base.reg0216_sli_splt.sli_splt = 0; in vepu540c_h265_set_split()
1139 regs->reg_base.reg0216_sli_splt.sli_splt_mode = 0; in vepu540c_h265_set_split()
1140 regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0; in vepu540c_h265_set_split()
1141 regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 0; in vepu540c_h265_set_split()
1142 regs->reg_base.reg0216_sli_splt.sli_flsh = 0; in vepu540c_h265_set_split()
1143 regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = 0; in vepu540c_h265_set_split()
1145 regs->reg_base.reg0217_sli_byte.sli_splt_byte = 0; in vepu540c_h265_set_split()
1146 regs->reg_base.reg0192_enc_pic.slen_fifo = 0; in vepu540c_h265_set_split()
1149 regs->reg_base.reg0216_sli_splt.sli_splt = 1; in vepu540c_h265_set_split()
1150 regs->reg_base.reg0216_sli_splt.sli_splt_mode = 0; in vepu540c_h265_set_split()
1151 regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0; in vepu540c_h265_set_split()
1152 regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 500; in vepu540c_h265_set_split()
1153 regs->reg_base.reg0216_sli_splt.sli_flsh = 1; in vepu540c_h265_set_split()
1154 regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = 0; in vepu540c_h265_set_split()
1156 regs->reg_base.reg0217_sli_byte.sli_splt_byte = cfg->split_arg; in vepu540c_h265_set_split()
1157 regs->reg_base.reg0192_enc_pic.slen_fifo = cfg->split_out ? 1 : 0; in vepu540c_h265_set_split()
1158 regs->reg_ctl.reg0008_int_en.vslc_done_en = regs->reg_base.reg0192_enc_pic.slen_fifo; in vepu540c_h265_set_split()
1170 regs->reg_base.reg0216_sli_splt.sli_splt = 1; in vepu540c_h265_set_split()
1171 regs->reg_base.reg0216_sli_splt.sli_splt_mode = 1; in vepu540c_h265_set_split()
1172 regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0; in vepu540c_h265_set_split()
1173 regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 500; in vepu540c_h265_set_split()
1174 regs->reg_base.reg0216_sli_splt.sli_flsh = 1; in vepu540c_h265_set_split()
1175 regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1; in vepu540c_h265_set_split()
1177 regs->reg_base.reg0217_sli_byte.sli_splt_byte = 0; in vepu540c_h265_set_split()
1178 regs->reg_base.reg0192_enc_pic.slen_fifo = cfg->split_out ? 1 : 0; in vepu540c_h265_set_split()
1181 (regs->reg_base.reg0192_enc_pic.slen_fifo && (slice_num > VEPU540C_SLICE_FIFO_LEN))) in vepu540c_h265_set_split()
1202 hevc_vepu540c_base *reg_base = ®s->reg_base; in hal_h265e_v540c_gen_regs() local
1261 reg_base->reg0196_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; in hal_h265e_v540c_gen_regs()
1262 reg_base->reg0197_src_fill.pic_wfill = (syn->pp.pic_width & 0x7) in hal_h265e_v540c_gen_regs()
1264 reg_base->reg0196_enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1; in hal_h265e_v540c_gen_regs()
1265 reg_base->reg0197_src_fill.pic_hfill = (syn->pp.pic_height & 0x7) in hal_h265e_v540c_gen_regs()
1268 reg_base->reg0192_enc_pic.enc_stnd = 1; //H265 in hal_h265e_v540c_gen_regs()
1269 …reg_base->reg0192_enc_pic.cur_frm_ref = !syn->sp.non_reference_flag; //current frame will be ref… in hal_h265e_v540c_gen_regs()
1270 reg_base->reg0192_enc_pic.bs_scp = 1; in hal_h265e_v540c_gen_regs()
1271 reg_base->reg0192_enc_pic.log2_ctu_num = mpp_ceil_log2(pic_wd32 * pic_h32); in hal_h265e_v540c_gen_regs()
1273 reg_base->reg0203_src_proc.src_mirr = 0; in hal_h265e_v540c_gen_regs()
1274 reg_base->reg0203_src_proc.src_rot = 0; in hal_h265e_v540c_gen_regs()
1279 reg_base->reg0248_sao_cfg.sao_lambda_multi = 5; in hal_h265e_v540c_gen_regs()
1281 vepu540c_h265_set_me_regs(ctx, syn, reg_base); in hal_h265e_v540c_gen_regs()
1283 reg_base->reg0232_rdo_cfg.chrm_spcl = 0; in hal_h265e_v540c_gen_regs()
1284 reg_base->reg0232_rdo_cfg.cu_inter_e = 0x0092; in hal_h265e_v540c_gen_regs()
1285 reg_base->reg0232_rdo_cfg.cu_intra_e = 0xe; in hal_h265e_v540c_gen_regs()
1286 reg_base->reg0232_rdo_cfg.lambda_qp_use_avg_cu16_flag = 1; in hal_h265e_v540c_gen_regs()
1287 reg_base->reg0232_rdo_cfg.yuvskip_calc_en = 1; in hal_h265e_v540c_gen_regs()
1288 reg_base->reg0232_rdo_cfg.atf_e = 1; in hal_h265e_v540c_gen_regs()
1289 reg_base->reg0232_rdo_cfg.atr_e = 1; in hal_h265e_v540c_gen_regs()
1292 reg_base->reg0232_rdo_cfg.ltm_col = 0; in hal_h265e_v540c_gen_regs()
1293 reg_base->reg0232_rdo_cfg.ltm_idx0l0 = 1; in hal_h265e_v540c_gen_regs()
1295 reg_base->reg0232_rdo_cfg.ltm_col = 0; in hal_h265e_v540c_gen_regs()
1296 reg_base->reg0232_rdo_cfg.ltm_idx0l0 = 0; in hal_h265e_v540c_gen_regs()
1299 reg_base->reg0232_rdo_cfg.ccwa_e = 1; in hal_h265e_v540c_gen_regs()
1300 reg_base->reg0232_rdo_cfg.scl_lst_sel = syn->pp.scaling_list_enabled_flag; in hal_h265e_v540c_gen_regs()
1301 reg_base->reg0236_synt_nal.nal_unit_type = h265e_get_nal_type(&syn->sp, ctx->frame_type); in hal_h265e_v540c_gen_regs()
1303 vepu540c_h265_set_hw_address(ctx, reg_base, task); in hal_h265e_v540c_gen_regs()
1306 vepu540c_h265_set_slice_regs(syn, reg_base); in hal_h265e_v540c_gen_regs()
1307 vepu540c_h265_set_ref_regs(syn, reg_base); in hal_h265e_v540c_gen_regs()
1360 cfg.reg = &hw_regs->reg_base; in hal_h265e_v540c_start()
1371 regs = (RK_U32*)(&hw_regs->reg_base); in hal_h265e_v540c_start()