Lines Matching refs:reg_base
370 p->osd_cfg.reg_base = &p->regs_sets->reg_osd; in hal_h264e_vepu580_init()
603 ctx->osd_cfg.reg_base = &ctx->regs_set->reg_osd; in hal_h264e_vepu580_get_task()
718 regs->reg_base.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu580_prep()
719 regs->reg_base.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu580_prep()
720 regs->reg_base.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu580_prep()
721 regs->reg_base.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu580_prep()
725 regs->reg_base.src_fmt.src_cfmt = hw_fmt; in setup_vepu580_prep()
726 regs->reg_base.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu580_prep()
727 regs->reg_base.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu580_prep()
728 regs->reg_base.src_fmt.out_fmt = (fmt == MPP_FMT_YUV400) ? 0 : 1; in setup_vepu580_prep()
731 regs->reg_base.src_fmt.src_range = 1; in setup_vepu580_prep()
733 regs->reg_base.src_fmt.src_range = (prep->range == MPP_FRAME_RANGE_JPEG) ? 1 : 0; in setup_vepu580_prep()
773 regs->reg_base.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu580_prep()
774 regs->reg_base.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu580_prep()
775 regs->reg_base.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu580_prep()
777 regs->reg_base.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu580_prep()
778 regs->reg_base.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu580_prep()
779 regs->reg_base.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu580_prep()
781 regs->reg_base.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; in setup_vepu580_prep()
782 regs->reg_base.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in setup_vepu580_prep()
783 regs->reg_base.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in setup_vepu580_prep()
785 regs->reg_base.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in setup_vepu580_prep()
786 regs->reg_base.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu580_prep()
787 regs->reg_base.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset; in setup_vepu580_prep()
791 regs->reg_base.src_udfy.csc_wgt_b2y = cfg.weight[0]; in setup_vepu580_prep()
792 regs->reg_base.src_udfy.csc_wgt_g2y = cfg.weight[1]; in setup_vepu580_prep()
793 regs->reg_base.src_udfy.csc_wgt_r2y = cfg.weight[2]; in setup_vepu580_prep()
795 regs->reg_base.src_udfu.csc_wgt_b2u = cfg.weight[3]; in setup_vepu580_prep()
796 regs->reg_base.src_udfu.csc_wgt_g2u = cfg.weight[4]; in setup_vepu580_prep()
797 regs->reg_base.src_udfu.csc_wgt_r2u = cfg.weight[5]; in setup_vepu580_prep()
799 regs->reg_base.src_udfv.csc_wgt_b2v = cfg.weight[6]; in setup_vepu580_prep()
800 regs->reg_base.src_udfv.csc_wgt_g2v = cfg.weight[7]; in setup_vepu580_prep()
801 regs->reg_base.src_udfv.csc_wgt_r2v = cfg.weight[8]; in setup_vepu580_prep()
803 regs->reg_base.src_udfo.csc_ofst_y = cfg.offset[0]; in setup_vepu580_prep()
804 regs->reg_base.src_udfo.csc_ofst_u = cfg.offset[1]; in setup_vepu580_prep()
805 regs->reg_base.src_udfo.csc_ofst_v = cfg.offset[2]; in setup_vepu580_prep()
808 regs->reg_base.src_proc.afbcd_en = MPP_FRAME_FMT_IS_FBC(fmt) ? 1 : 0; in setup_vepu580_prep()
809 regs->reg_base.src_strd0.src_strd0 = y_stride; in setup_vepu580_prep()
810 regs->reg_base.src_strd1.src_strd1 = c_stride; in setup_vepu580_prep()
812 regs->reg_base.src_proc.src_mirr = prep->mirroring > 0; in setup_vepu580_prep()
813 regs->reg_base.src_proc.src_rot = prep->rotation; in setup_vepu580_prep()
814 regs->reg_base.src_proc.txa_en = 0; in setup_vepu580_prep()
816 regs->reg_base.sli_cfg.sli_crs_en = 1; in setup_vepu580_prep()
818 regs->reg_base.pic_ofst.pic_ofst_y = 0; in setup_vepu580_prep()
819 regs->reg_base.pic_ofst.pic_ofst_x = 0; in setup_vepu580_prep()
839 regs->reg_base.enc_pic.cur_frm_ref = 1; in vepu580_h264e_save_pass1_patch()
840 regs->reg_base.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1); in vepu580_h264e_save_pass1_patch()
841 regs->reg_base.rfpw_b_addr = regs->reg_base.rfpw_h_addr; in vepu580_h264e_save_pass1_patch()
842 regs->reg_base.enc_pic.rec_fbc_dis = 1; in vepu580_h264e_save_pass1_patch()
847 regs->reg_base.sli_splt.sli_splt = 0; in vepu580_h264e_save_pass1_patch()
848 regs->reg_base.enc_pic.slen_fifo = 0; in vepu580_h264e_save_pass1_patch()
863 regs->reg_base.src_fmt.src_cfmt = VEPU5xx_FMT_YUV420SP; in vepu580_h264e_use_pass1_patch()
864 regs->reg_base.src_fmt.alpha_swap = 0; in vepu580_h264e_use_pass1_patch()
865 regs->reg_base.src_fmt.rbuv_swap = 0; in vepu580_h264e_use_pass1_patch()
866 regs->reg_base.src_fmt.out_fmt = 1; in vepu580_h264e_use_pass1_patch()
868 regs->reg_base.src_proc.afbcd_en = 0; in vepu580_h264e_use_pass1_patch()
869 regs->reg_base.src_strd0.src_strd0 = hor_stride; in vepu580_h264e_use_pass1_patch()
870 regs->reg_base.src_strd1.src_strd1 = hor_stride; in vepu580_h264e_use_pass1_patch()
872 regs->reg_base.src_proc.src_mirr = 0; in vepu580_h264e_use_pass1_patch()
873 regs->reg_base.src_proc.src_rot = 0; in vepu580_h264e_use_pass1_patch()
874 regs->reg_base.src_proc.txa_en = 0; in vepu580_h264e_use_pass1_patch()
876 regs->reg_base.pic_ofst.pic_ofst_y = 0; in vepu580_h264e_use_pass1_patch()
877 regs->reg_base.pic_ofst.pic_ofst_x = 0; in vepu580_h264e_use_pass1_patch()
880 regs->reg_base.adr_src0 = fd_in; in vepu580_h264e_use_pass1_patch()
881 regs->reg_base.adr_src1 = fd_in; in vepu580_h264e_use_pass1_patch()
882 regs->reg_base.adr_src2 = fd_in; in vepu580_h264e_use_pass1_patch()
896 regs->reg_base.enc_pic.enc_stnd = 0; in setup_vepu580_codec()
897 regs->reg_base.enc_pic.cur_frm_ref = slice->nal_reference_idc > 0; in setup_vepu580_codec()
898 regs->reg_base.enc_pic.bs_scp = 1; in setup_vepu580_codec()
900 regs->reg_base.synt_nal.nal_ref_idc = slice->nal_reference_idc; in setup_vepu580_codec()
901 regs->reg_base.synt_nal.nal_unit_type = slice->nalu_type; in setup_vepu580_codec()
903 regs->reg_base.synt_sps.max_fnum = sps->log2_max_frame_num_minus4; in setup_vepu580_codec()
904 regs->reg_base.synt_sps.drct_8x8 = sps->direct8x8_inference; in setup_vepu580_codec()
905 regs->reg_base.synt_sps.mpoc_lm4 = sps->log2_max_poc_lsb_minus4; in setup_vepu580_codec()
907 regs->reg_base.synt_pps.etpy_mode = pps->entropy_coding_mode; in setup_vepu580_codec()
908 regs->reg_base.synt_pps.trns_8x8 = pps->transform_8x8_mode; in setup_vepu580_codec()
909 regs->reg_base.synt_pps.csip_flag = pps->constrained_intra_pred; in setup_vepu580_codec()
910 regs->reg_base.synt_pps.num_ref0_idx = pps->num_ref_idx_l0_default_active - 1; in setup_vepu580_codec()
911 regs->reg_base.synt_pps.num_ref1_idx = pps->num_ref_idx_l1_default_active - 1; in setup_vepu580_codec()
912 regs->reg_base.synt_pps.pic_init_qp = pps->pic_init_qp; in setup_vepu580_codec()
913 regs->reg_base.synt_pps.cb_ofst = pps->chroma_qp_index_offset; in setup_vepu580_codec()
914 regs->reg_base.synt_pps.cr_ofst = pps->second_chroma_qp_index_offset; in setup_vepu580_codec()
915 regs->reg_base.synt_pps.wght_pred = pps->weighted_pred; in setup_vepu580_codec()
916 regs->reg_base.synt_pps.dbf_cp_flg = pps->deblocking_filter_control; in setup_vepu580_codec()
918 regs->reg_base.synt_sli0.sli_type = (slice->slice_type == H264_I_SLICE) ? (2) : (0); in setup_vepu580_codec()
919 regs->reg_base.synt_sli0.pps_id = slice->pic_parameter_set_id; in setup_vepu580_codec()
920 regs->reg_base.synt_sli0.drct_smvp = 0; in setup_vepu580_codec()
921 regs->reg_base.synt_sli0.num_ref_ovrd = slice->num_ref_idx_override; in setup_vepu580_codec()
922 regs->reg_base.synt_sli0.cbc_init_idc = slice->cabac_init_idc; in setup_vepu580_codec()
923 regs->reg_base.synt_sli0.frm_num = slice->frame_num; in setup_vepu580_codec()
925 …regs->reg_base.synt_sli1.idr_pid = (slice->slice_type == H264_I_SLICE) ? slice->idr_pic_id … in setup_vepu580_codec()
926 regs->reg_base.synt_sli1.poc_lsb = slice->pic_order_cnt_lsb; in setup_vepu580_codec()
929 regs->reg_base.synt_sli2.dis_dblk_idc = slice->disable_deblocking_filter_idc; in setup_vepu580_codec()
930 regs->reg_base.synt_sli2.sli_alph_ofst = slice->slice_alpha_c0_offset_div2; in setup_vepu580_codec()
938 regs->reg_base.synt_sli2.ref_list0_rodr = 1; in setup_vepu580_codec()
939 regs->reg_base.synt_sli2.rodr_pic_idx = rplmo.modification_of_pic_nums_idc; in setup_vepu580_codec()
944 regs->reg_base.synt_sli2.rodr_pic_num = rplmo.abs_diff_pic_num_minus1; in setup_vepu580_codec()
947 regs->reg_base.synt_sli2.rodr_pic_num = rplmo.long_term_pic_idx; in setup_vepu580_codec()
956 regs->reg_base.synt_sli2.ref_list0_rodr = 0; in setup_vepu580_codec()
957 regs->reg_base.synt_sli2.rodr_pic_idx = 0; in setup_vepu580_codec()
958 regs->reg_base.synt_sli2.rodr_pic_num = 0; in setup_vepu580_codec()
963 regs->reg_base.synt_refm0.nopp_flg = 0; in setup_vepu580_codec()
964 regs->reg_base.synt_refm0.ltrf_flg = 0; in setup_vepu580_codec()
965 regs->reg_base.synt_refm0.arpm_flg = 0; in setup_vepu580_codec()
966 regs->reg_base.synt_refm0.mmco4_pre = 0; in setup_vepu580_codec()
967 regs->reg_base.synt_refm0.mmco_type0 = 0; in setup_vepu580_codec()
968 regs->reg_base.synt_refm0.mmco_parm0 = 0; in setup_vepu580_codec()
969 regs->reg_base.synt_refm0.mmco_type1 = 0; in setup_vepu580_codec()
970 regs->reg_base.synt_refm1.mmco_parm1 = 0; in setup_vepu580_codec()
971 regs->reg_base.synt_refm0.mmco_type2 = 0; in setup_vepu580_codec()
972 regs->reg_base.synt_refm1.mmco_parm2 = 0; in setup_vepu580_codec()
973 regs->reg_base.synt_refm2.long_term_frame_idx0 = 0; in setup_vepu580_codec()
974 regs->reg_base.synt_refm2.long_term_frame_idx1 = 0; in setup_vepu580_codec()
975 regs->reg_base.synt_refm2.long_term_frame_idx2 = 0; in setup_vepu580_codec()
981 regs->reg_base.synt_refm0.nopp_flg = slice->no_output_of_prior_pics; in setup_vepu580_codec()
982 regs->reg_base.synt_refm0.ltrf_flg = slice->long_term_reference_flag; in setup_vepu580_codec()
987 regs->reg_base.synt_refm0.arpm_flg = 1; in setup_vepu580_codec()
1022 regs->reg_base.synt_refm0.mmco_type0 = type; in setup_vepu580_codec()
1023 regs->reg_base.synt_refm0.mmco_parm0 = param_0; in setup_vepu580_codec()
1024 regs->reg_base.synt_refm2.long_term_frame_idx0 = param_1; in setup_vepu580_codec()
1058 regs->reg_base.synt_refm0.mmco_type1 = type; in setup_vepu580_codec()
1059 regs->reg_base.synt_refm1.mmco_parm1 = param_0; in setup_vepu580_codec()
1060 regs->reg_base.synt_refm2.long_term_frame_idx1 = param_1; in setup_vepu580_codec()
1094 regs->reg_base.synt_refm0.mmco_type2 = type; in setup_vepu580_codec()
1095 regs->reg_base.synt_refm1.mmco_parm2 = param_0; in setup_vepu580_codec()
1096 regs->reg_base.synt_refm2.long_term_frame_idx2 = param_1; in setup_vepu580_codec()
1117 regs->reg_base.iprd_csts.vthd_y = 9; in setup_vepu580_rdo_pred()
1118 regs->reg_base.iprd_csts.vthd_c = 63; in setup_vepu580_rdo_pred()
1120 regs->reg_base.rdo_cfg.rect_size = (sps->profile_idc == H264_PROFILE_BASELINE && in setup_vepu580_rdo_pred()
1122 regs->reg_base.rdo_cfg.inter_4x4 = 1; in setup_vepu580_rdo_pred()
1123 regs->reg_base.rdo_cfg.vlc_lmt = (sps->profile_idc < H264_PROFILE_MAIN) && in setup_vepu580_rdo_pred()
1125 regs->reg_base.rdo_cfg.chrm_spcl = 1; in setup_vepu580_rdo_pred()
1126 regs->reg_base.rdo_cfg.rdo_mask = 0; in setup_vepu580_rdo_pred()
1127 regs->reg_base.rdo_cfg.ccwa_e = 1; in setup_vepu580_rdo_pred()
1128 regs->reg_base.rdo_cfg.scl_lst_sel = pps->pic_scaling_matrix_present; in setup_vepu580_rdo_pred()
1129 regs->reg_base.rdo_cfg.atr_e = 1; in setup_vepu580_rdo_pred()
1130 regs->reg_base.rdo_cfg.atf_intra_e = 1; in setup_vepu580_rdo_pred()
1289 regs->reg_base.enc_pic.pic_qp = qp_target; in setup_vepu580_rc_base()
1290 regs->reg_base.rc_qp.rc_max_qp = qp_target; in setup_vepu580_rc_base()
1291 regs->reg_base.rc_qp.rc_min_qp = qp_target; in setup_vepu580_rc_base()
1303 regs->reg_base.enc_pic.pic_qp = qp_target; in setup_vepu580_rc_base()
1304 regs->reg_base.rc_cfg.rc_en = 1; in setup_vepu580_rc_base()
1305 regs->reg_base.rc_cfg.aq_en = 1; in setup_vepu580_rc_base()
1306 regs->reg_base.rc_cfg.aq_mode = 0; in setup_vepu580_rc_base()
1307 regs->reg_base.rc_cfg.rc_ctu_num = mb_w; in setup_vepu580_rc_base()
1308 regs->reg_base.rc_qp.rc_qp_range = (slice->slice_type == H264_I_SLICE) ? in setup_vepu580_rc_base()
1310 regs->reg_base.rc_qp.rc_max_qp = qp_max; in setup_vepu580_rc_base()
1311 regs->reg_base.rc_qp.rc_min_qp = qp_min; in setup_vepu580_rc_base()
1312 regs->reg_base.rc_tgt.ctu_ebit = mb_target_bits_mul_16; in setup_vepu580_rc_base()
1346 regs->reg_base.rc_qp.rc_qp_range = 0; in setup_vepu580_rc_base()
1370 regs->reg_base.adr_src0 = fd_in; in setup_vepu580_io_buf()
1371 regs->reg_base.adr_src1 = fd_in; in setup_vepu580_io_buf()
1372 regs->reg_base.adr_src2 = fd_in; in setup_vepu580_io_buf()
1374 regs->reg_base.bsbb_addr = fd_out; in setup_vepu580_io_buf()
1375 regs->reg_base.bsbr_addr = fd_out; in setup_vepu580_io_buf()
1376 regs->reg_base.adr_bsbs = fd_out; in setup_vepu580_io_buf()
1377 regs->reg_base.bsbt_addr = fd_out; in setup_vepu580_io_buf()
1542 regs->reg_base.me_rnge.cme_srch_v = 1; in setup_vepu580_intra_refresh()
1553 regs->reg_base.me_rnge.cme_srch_h = 1; in setup_vepu580_intra_refresh()
1563 regs->reg_base.enc_pic.roi_en = 1; in setup_vepu580_intra_refresh()
1564 regs->reg_base.roi_addr = base_cfg_fd; in setup_vepu580_intra_refresh()
1590 regs->reg_base.enc_pic.roi_en = 1; in setup_vepu580_roi()
1591 regs->reg_base.roi_addr = mpp_buffer_get_fd(cfg->base_cfg_buf); in setup_vepu580_roi()
1598 regs->reg_base.roi_qp_addr = mpp_buffer_get_fd(cfg->qp_cfg_buf); in setup_vepu580_roi()
1599 regs->reg_base.roi_en.roi_qp_en = 1; in setup_vepu580_roi()
1607 regs->reg_base.qoi_amv_addr = mpp_buffer_get_fd(cfg->amv_cfg_buf); in setup_vepu580_roi()
1608 regs->reg_base.roi_en.roi_amv_en = 1; in setup_vepu580_roi()
1616 regs->reg_base.qoi_mv_addr = mpp_buffer_get_fd(cfg->mv_cfg_buf); in setup_vepu580_roi()
1617 regs->reg_base.roi_en.roi_mv_en = 1; in setup_vepu580_roi()
1646 regs->reg_base.rfpw_h_addr = fd; in setup_vepu580_recn_refr()
1647 regs->reg_base.rfpw_b_addr = fd; in setup_vepu580_recn_refr()
1648 regs->reg_base.dspw_addr = mpp_buffer_get_fd(buf_thumb); in setup_vepu580_recn_refr()
1659 regs->reg_base.rfpr_h_addr = fd; in setup_vepu580_recn_refr()
1660 regs->reg_base.rfpr_b_addr = fd; in setup_vepu580_recn_refr()
1661 regs->reg_base.dspr_addr = mpp_buffer_get_fd(buf_thumb); in setup_vepu580_recn_refr()
1678 regs->reg_base.sli_splt.sli_splt = 0; in setup_vepu580_split()
1679 regs->reg_base.sli_splt.sli_splt_mode = 0; in setup_vepu580_split()
1680 regs->reg_base.sli_splt.sli_splt_cpst = 0; in setup_vepu580_split()
1681 regs->reg_base.sli_splt.sli_max_num_m1 = 0; in setup_vepu580_split()
1682 regs->reg_base.sli_splt.sli_flsh = 0; in setup_vepu580_split()
1683 regs->reg_base.sli_cnum.sli_splt_cnum_m1 = 0; in setup_vepu580_split()
1685 regs->reg_base.sli_byte.sli_splt_byte = 0; in setup_vepu580_split()
1686 regs->reg_base.enc_pic.slen_fifo = 0; in setup_vepu580_split()
1689 regs->reg_base.sli_splt.sli_splt = 1; in setup_vepu580_split()
1690 regs->reg_base.sli_splt.sli_splt_mode = 0; in setup_vepu580_split()
1691 regs->reg_base.sli_splt.sli_splt_cpst = 0; in setup_vepu580_split()
1692 regs->reg_base.sli_splt.sli_max_num_m1 = 500; in setup_vepu580_split()
1693 regs->reg_base.sli_splt.sli_flsh = 1; in setup_vepu580_split()
1694 regs->reg_base.sli_cnum.sli_splt_cnum_m1 = 0; in setup_vepu580_split()
1696 regs->reg_base.sli_byte.sli_splt_byte = cfg->split_arg; in setup_vepu580_split()
1697 regs->reg_base.enc_pic.slen_fifo = cfg->split_out ? 1 : 0; in setup_vepu580_split()
1698 regs->reg_ctl.int_en.slc_done_en = regs->reg_base.enc_pic.slen_fifo; in setup_vepu580_split()
1705 regs->reg_base.sli_splt.sli_splt = 1; in setup_vepu580_split()
1706 regs->reg_base.sli_splt.sli_splt_mode = 1; in setup_vepu580_split()
1707 regs->reg_base.sli_splt.sli_splt_cpst = 0; in setup_vepu580_split()
1708 regs->reg_base.sli_splt.sli_max_num_m1 = 500; in setup_vepu580_split()
1709 regs->reg_base.sli_splt.sli_flsh = 1; in setup_vepu580_split()
1710 regs->reg_base.sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1; in setup_vepu580_split()
1712 regs->reg_base.sli_byte.sli_splt_byte = 0; in setup_vepu580_split()
1713 regs->reg_base.enc_pic.slen_fifo = cfg->split_out ? 1 : 0; in setup_vepu580_split()
1716 (regs->reg_base.enc_pic.slen_fifo && (slice_num > VEPU580_SLICE_FIFO_LEN))) in setup_vepu580_split()
1730 Vepu580BaseCfg *base_regs = ®s->reg_base; in calc_cime_parameter()
1859 regs->reg_base.me_rnge.cme_srch_h = cime_blk_w_max / 4; in setup_vepu580_me()
1860 regs->reg_base.me_rnge.cme_srch_v = cime_blk_h_max / 4; in setup_vepu580_me()
1861 regs->reg_base.me_rnge.rme_srch_h = 7; in setup_vepu580_me()
1862 regs->reg_base.me_rnge.rme_srch_v = 5; in setup_vepu580_me()
1863 regs->reg_base.me_rnge.dlt_frm_num = 0; in setup_vepu580_me()
1866 regs->reg_base.me_cfg.pmv_mdst_h = 0; in setup_vepu580_me()
1867 regs->reg_base.me_cfg.pmv_mdst_v = 0; in setup_vepu580_me()
1869 regs->reg_base.me_cfg.pmv_mdst_h = 5; in setup_vepu580_me()
1870 regs->reg_base.me_cfg.pmv_mdst_v = 5; in setup_vepu580_me()
1872 …regs->reg_base.me_cfg.mv_limit = (sps->level_idc > 20) ? 2 : ((sps->level_idc >= 11) ? 1 : 0);//2; in setup_vepu580_me()
1873 regs->reg_base.me_cfg.pmv_num = 2; in setup_vepu580_me()
1874 regs->reg_base.me_cfg.rme_dis = 0; in setup_vepu580_me()
1875 regs->reg_base.me_cfg.fme_dis = 0; in setup_vepu580_me()
1876 regs->reg_base.me_cfg.lvl4_ovrd_en = 0; in setup_vepu580_me()
2057 regs->reg_base.ebufb_addr = 0; in setup_vepu580_ext_line_buf()
2058 regs->reg_base.ebufb_addr = 0; in setup_vepu580_ext_line_buf()
2065 regs->reg_base.ebuft_addr = fd; in setup_vepu580_ext_line_buf()
2066 regs->reg_base.ebufb_addr = fd; in setup_vepu580_ext_line_buf()
2088 Vepu580BaseCfg *reg_base = &ctx->regs_set->reg_base; in setup_vepu580_dual_core() local
2101 reg_base->dual_core.dchs_txid = ctx->curr_idx; in setup_vepu580_dual_core()
2102 reg_base->dual_core.dchs_rxid = ctx->prev_idx; in setup_vepu580_dual_core()
2103 reg_base->dual_core.dchs_txe = 1; in setup_vepu580_dual_core()
2104 reg_base->dual_core.dchs_rxe = dchs_rxe; in setup_vepu580_dual_core()
2105 reg_base->dual_core.dchs_ofst = dchs_ofst; in setup_vepu580_dual_core()
2152 regs->reg_base.meiw_addr = task->md_info ? mpp_buffer_get_fd(task->md_info) : 0; in hal_h264e_vepu580_gen_regs()
2153 regs->reg_base.enc_pic.mei_stor = task->md_info ? 1 : 0; in hal_h264e_vepu580_gen_regs()
2154 regs->reg_base.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame); in hal_h264e_vepu580_gen_regs()
2155 regs->reg_base.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame); in hal_h264e_vepu580_gen_regs()
2221 wr_cfg.reg = ®s->reg_base; in hal_h264e_vepu580_start()
2222 wr_cfg.size = sizeof(regs->reg_base); in hal_h264e_vepu580_start()