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Searched refs:rank (Results 1 – 25 of 88) sorted by relevance

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/rk3399_rockchip-uboot/arch/x86/cpu/quark/
H A Dmrc_util.h84 void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane);
86 void set_rcvn(uint8_t channel, uint8_t rank,
88 uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane);
89 void set_rdqs(uint8_t channel, uint8_t rank,
91 uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
92 void set_wdqs(uint8_t channel, uint8_t rank,
94 uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
95 void set_wdq(uint8_t channel, uint8_t rank,
97 uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane);
100 void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count);
[all …]
H A Dmrc_util.c127 void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane) in training_message() argument
130 DPF(D_INFO, "CH%01X RK%01X BL%01X\n", channel, rank, byte_lane); in training_message()
138 void set_rcvn(uint8_t channel, uint8_t rank, in set_rcvn() argument
148 channel, rank, byte_lane, pi_count); in set_rcvn()
201 training_message(channel, rank, byte_lane); in set_rcvn()
214 uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane) in get_rcvn() argument
262 void set_rdqs(uint8_t channel, uint8_t rank, in set_rdqs() argument
271 channel, rank, byte_lane, pi_count); in set_rdqs()
287 training_message(channel, rank, byte_lane); in set_rdqs()
300 uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane) in get_rdqs() argument
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H A Dsmc.c1156 uint8_t twr, wl, rank; in perform_jedec_init() local
1196 for (rank = 0; rank < NUM_RANKS; rank++) { in perform_jedec_init()
1198 if ((mrc_params->rank_enables & (1 << rank)) == 0) in perform_jedec_init()
1201 dram_init_command(DCMD_NOP(rank)); in perform_jedec_init()
1305 for (rank = 0; rank < NUM_RANKS; rank++) { in perform_jedec_init()
1307 if ((mrc_params->rank_enables & (1 << rank)) == 0) in perform_jedec_init()
1310 emrs2_cmd |= (rank << 22); in perform_jedec_init()
1313 emrs3_cmd |= (rank << 22); in perform_jedec_init()
1316 emrs1_cmd |= (rank << 22); in perform_jedec_init()
1319 mrs0_cmd |= (rank << 22); in perform_jedec_init()
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/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_pctl_px30.c16 void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num) in pctl_read_mr() argument
18 writel((rank << 4) | (1 << 0), pctl_base + DDR_PCTL2_MRCTRL0); in pctl_read_mr()
32 int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg, in pctl_write_mr() argument
38 writel((mr_num << 12) | (rank << 4) | (0 << 0), in pctl_write_mr()
42 writel((rank << 4) | (0 << 0), in pctl_write_mr()
61 int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate, in pctl_write_vrefdq() argument
84 pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype); in pctl_write_vrefdq()
87 pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype); in pctl_write_vrefdq()
89 pctl_write_mr(pctl_base, rank, 6, value | (0 << 7), dramtype); in pctl_write_vrefdq()
142 void send_a_refresh(void __iomem *pctl_base, u32 rank) in send_a_refresh() argument
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H A Dsdram_rk3188.c312 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, in send_command() argument
315 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
322 u32 rank, u32 cmd, u32 ma, u32 op) in send_command_op() argument
324 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | in send_command_op()
422 u32 rank; in data_training() local
433 rank = sdram_params->ch[channel].rank | 1; in data_training()
447 while ((readl(&publ->datx8[0].dxgsr[0]) & rank) in data_training()
448 != rank) in data_training()
450 while ((readl(&publ->datx8[1].dxgsr[0]) & rank) in data_training()
451 != rank) in data_training()
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H A Dsdram_rk3288.c370 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, in send_command() argument
373 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
380 u32 rank, u32 cmd, u32 ma, u32 op) in send_command_op() argument
382 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | in send_command_op()
480 u32 rank; in data_training() local
491 rank = sdram_params->ch[channel].rank | 1; in data_training()
505 while ((readl(&publ->datx8[0].dxgsr[0]) & rank) in data_training()
506 != rank) in data_training()
508 while ((readl(&publ->datx8[1].dxgsr[0]) & rank) in data_training()
509 != rank) in data_training()
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H A Dsdram_common.c84 if (cap_info->rank > 1) { in sdram_print_ddr_info()
93 if (cap_info->rank > 2) { in sdram_print_ddr_info()
110 printdec(cap_info->rank); in sdram_print_ddr_info()
146 if (cap_info->rank >= 2) in sdram_get_cs_cap()
152 if (cap_info->rank == 4) { in sdram_get_cs_cap()
190 *p_os_reg2 |= SYS_REG_ENC_RANK(cap_info->rank, channel); in sdram_org_config()
216 SYS_REG_ENC_CH0_2_RANK_V3(cap_info->rank, in sdram_org_config_v3()
219 *p_os_reg2 |= SYS_REG_ENC_CH1_3_RANK(cap_info->rank); in sdram_org_config_v3()
230 if ((channel == 0 || channel == 2) && cap_info->rank > 2) { in sdram_org_config_v3()
361 cs = cap_info->rank; in sdram_detect_dbw()
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H A Dsdram_rk3399.c160 cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1; in set_memory_map()
190 if (sdram_ch->cap_info.rank == 1 && in set_memory_map()
1383 u32 rank) in select_per_cs_training_index() argument
1393 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24); in select_per_cs_training_index()
1394 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24); in select_per_cs_training_index()
1395 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24); in select_per_cs_training_index()
1396 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24); in select_per_cs_training_index()
1436 u32 rank = sdram_params->ch[channel].cap_info.rank; in data_training_ca() local
1443 rank_mask = (rank == 1) ? 0x5 : 0xf; in data_training_ca()
1445 rank_mask = (rank == 1) ? 0x1 : 0x3; in data_training_ca()
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H A Dsdram_rv1126.c406 cs = cap_info->rank; in calculate_ddrconfig()
560 if (cap_info->rank == 1) in set_ctl_address_map()
1315 u32 read_mr(struct dram_info *dram, u32 rank, u32 byte, u32 mr_num, u32 dramtype) in read_mr() argument
1323 pctl_read_mr(pctl_base, rank, mr_num); in read_mr()
1481 static u32 get_min_value(struct dram_info *dram, u32 signal, u32 rank) in get_min_value() argument
1496 for (j = offset; j < offset + rank * 4; j++) { in get_min_value()
1533 int delta_dif, int delta_sig, u32 rank) in modify_dq_deskew() argument
1546 for (j = offset; j < (offset + rank * 4); j++) { in modify_dq_deskew()
1640 u32 rank) in data_training_wl() argument
1659 if ((dramtype == DDR3 || dramtype == DDR4) && rank == 2) in data_training_wl()
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/rk3399_rockchip-uboot/arch/arm/mach-uniphier/dram/
H A Dcmd_ddrphy.c141 int rank; in __wld_dump() local
145 for (rank = 0; rank < 4; rank++) { in __wld_dump()
146 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */ in __wld_dump()
147 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */ in __wld_dump()
164 int rank; in __dqsgd_dump() local
168 for (rank = 0; rank < 4; rank++) { in __dqsgd_dump()
169 u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */ in __dqsgd_dump()
170 u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */ in __dqsgd_dump()
H A Dcmd_ddrmphy.c167 int rank; in __wld_dump() local
171 for (rank = 0; rank < 4; rank++) { in __wld_dump()
172 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */ in __wld_dump()
173 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */ in __wld_dump()
190 int rank; in __dqsgd_dump() local
194 for (rank = 0; rank < 4; rank++) { in __dqsgd_dump()
195 u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */ in __dqsgd_dump()
196 u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */ in __dqsgd_dump()
H A Dddrphy-training.c18 void ddrphy_prepare_training(void __iomem *phy_base, int rank) in ddrphy_prepare_training() argument
28 tmp |= (1 << (PHY_DX_GCR_WLRKEN_SHIFT + rank)) & in ddrphy_prepare_training()
37 tmp |= (rank << PHY_DTCR_DTRANK_SHIFT) & PHY_DTCR_DTRANK_MASK; in ddrphy_prepare_training()
42 tmp |= (1 << (PHY_DTCR_RANKEN_SHIFT + rank)) & PHY_DTCR_RANKEN_MASK; in ddrphy_prepare_training()
H A Dddrphy-init.h14 void ddrphy_prepare_training(void __iomem *phy_base, int rank);
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a33.c27 u8 rank; member
43 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), in mctl_set_cr()
49 u8 orig_rank = para->rank; in auto_detect_dram_size()
56 para->rank = 1; in auto_detect_dram_size()
73 para->rank = orig_rank; in auto_detect_dram_size()
185 if (para->rank == 2) in mctl_data_train_cfg()
233 para->rank = 2; in mctl_channel_init()
260 para->rank = 1; in mctl_channel_init()
338 .rank = 1, in sunxi_dram_init()
355 if (para.rank == 2) in sunxi_dram_init()
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H A Ddram_sun8i_a83t.c25 u8 rank; member
42 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), in mctl_set_cr()
48 u8 orig_rank = para->rank; in auto_detect_dram_size()
55 para->rank = 1; in auto_detect_dram_size()
72 para->rank = orig_rank; in auto_detect_dram_size()
217 if (para->rank == 2) in mctl_data_train_cfg()
316 para->rank = 2; in mctl_channel_init()
352 para->rank = 1; in mctl_channel_init()
416 para->rank = 2; in mctl_sys_init()
436 .rank = 1, in sunxi_dram_init()
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H A Ddram_sun6i.c25 u8 rank; member
92 static bool mctl_rank_detect(u32 *gsr0, int rank) in mctl_rank_detect() argument
94 const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank; in mctl_rank_detect()
95 const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank; in mctl_rank_detect()
167 para->rank = 1; in mctl_channel_init()
275 MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr); in mctl_com_init()
340 .rank = 2, in sunxi_dram_init()
408 MCTL_CR_RANK(para.rank)); in sunxi_dram_init()
410 return 1 << (para.rank + para.rows + bank + columns + para.chan + bus); in sunxi_dram_init()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/
H A Dsdram.c23 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
38 rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & in rockchip_sdram_size()
89 if (rank > 1) in rockchip_sdram_size()
95 if (rank > 1) in rockchip_sdram_size()
98 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
103 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3066/
H A Dsdram_rk3066.c301 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, in send_command() argument
304 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
311 u32 rank, u32 cmd, u32 ma, u32 op) in send_command_op() argument
313 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | in send_command_op()
409 u32 rank; in data_training() local
420 rank = sdram_params->ch[channel].rank | 1; in data_training()
434 while ((readl(&publ->datx8[0].dxgsr[0]) & rank) in data_training()
435 != rank) in data_training()
437 while ((readl(&publ->datx8[1].dxgsr[0]) & rank) in data_training()
438 != rank) in data_training()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c444 u32 rank, u32 cmd, u32 arg) in send_command() argument
446 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
655 if (config.rank == 2) { in dram_cfg_rbc()
704 if (config.rank > 1) in sdram_all_config()
709 (config.rank - 1) << DDR_RANK_CNT_SHIFT | in sdram_all_config()
721 u32 size, os_reg, cs0_row, cs1_row, col, bank, rank; in sdram_size() local
730 rank = 1 + ((os_reg >> DDR_RANK_CNT_SHIFT) & DDR_RANK_CNT_MASK); in sdram_size()
735 if (rank > 1) in sdram_size()
/rk3399_rockchip-uboot/drivers/gpio/
H A Dlpc32xx_gpio.c112 int port, rank, mask, value; in lpc32xx_gpio_get_value() local
140 rank = GPIO_TO_RANK(offset); in lpc32xx_gpio_get_value()
143 return (value & mask) >> rank; in lpc32xx_gpio_get_value()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_pctl_px30.h253 void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num);
254 int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,
256 int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate,
/rk3399_rockchip-uboot/board/rockchip/evb_rk3036/
H A Devb_rk3036.c19 config->rank = 2; in get_ddr_config()
/rk3399_rockchip-uboot/board/rockchip/kylin_rk3036/
H A Dkylin_rk3036.c20 config->rank = 1; in get_ddr_config()
/rk3399_rockchip-uboot/arch/arm/mach-keystone/
H A Dddr3_spd.c136 u8 rank; member
179 spd->rank = ((buf->organization & 0x38) >> 3) + 1; in ddrtimingcalculation()
180 if (spd->rank > 2) in ddrtimingcalculation()
359 spd_cb->phy_cfg.dtcr = (spd->rank == 2) ? 0x730035C7 : 0x710035C7; in init_ddr3param()
375 if (spd->rank == 2) in init_ddr3param()
401 spd_cb->emif_cfg.zqcfg = (spd->rank == 2) ? 0xF0073200 : 0x70073200; in init_ddr3param()
/rk3399_rockchip-uboot/drivers/ram/rockchip/sdram_inc/rk3308/
H A Dsdram-rk3308-ddr2-detect-393.inc9 .rank = 0x1,

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