xref: /rk3399_rockchip-uboot/arch/arm/mach-uniphier/dram/ddrphy-init.h (revision 9f375f655fa54f88fdbe35d3f0c3bd6c1a91671b)
1*6dd34ae4SMasahiro Yamada /*
2*6dd34ae4SMasahiro Yamada  * Copyright (C) 2016 Socionext Inc.
3*6dd34ae4SMasahiro Yamada  *
4*6dd34ae4SMasahiro Yamada  * SPDX-License-Identifier:	GPL-2.0+
5*6dd34ae4SMasahiro Yamada  */
6*6dd34ae4SMasahiro Yamada 
7*6dd34ae4SMasahiro Yamada #ifndef ARCH_DDRPHY_INIT_H
8*6dd34ae4SMasahiro Yamada #define ARCH_DDRPHY_INTT_H
9*6dd34ae4SMasahiro Yamada 
10*6dd34ae4SMasahiro Yamada #include <linux/compiler.h>
11*6dd34ae4SMasahiro Yamada #include <linux/types.h>
12*6dd34ae4SMasahiro Yamada 
13*6dd34ae4SMasahiro Yamada int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus);
14*6dd34ae4SMasahiro Yamada void ddrphy_prepare_training(void __iomem *phy_base, int rank);
15*6dd34ae4SMasahiro Yamada int ddrphy_training(void __iomem *phy_base);
16*6dd34ae4SMasahiro Yamada 
17*6dd34ae4SMasahiro Yamada #endif /* ARCH_DDRPHY_INT_H */
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