406 	cs = cap_info->rank;  in calculate_ddrconfig()
560 	if (cap_info->rank == 1)  in set_ctl_address_map()
1315 u32 read_mr(struct dram_info *dram, u32 rank, u32 byte, u32 mr_num, u32 dramtype)  in read_mr()  argument
1323 	pctl_read_mr(pctl_base, rank, mr_num);  in read_mr()
1481 static u32 get_min_value(struct dram_info *dram, u32 signal, u32 rank)  in get_min_value()  argument
1496 		for (j = offset; j < offset + rank * 4; j++) {  in get_min_value()
1533 			     int delta_dif, int delta_sig, u32 rank)  in modify_dq_deskew()  argument
1546 	for (j = offset; j < (offset + rank * 4); j++) {  in modify_dq_deskew()
1640 			    u32 rank)  in data_training_wl()  argument
1659 	if ((dramtype == DDR3 || dramtype == DDR4) && rank == 2)  in data_training_wl()
1693 	if ((dramtype == DDR3 || dramtype == DDR4) && rank == 2)  in data_training_wl()
1952 				       sdram_params->ch.cap_info.rank);  in data_training()
1999 	if (sdram_params->ch.cap_info.rank == 2)  in get_wrlvl_val()
2112 	for (j = 0; j < sdram_params->ch.cap_info.rank; j++) {  in high_freq_training()
2119 		   (int)(sdram_params->ch.cap_info.rank * (1 << sdram_params->ch.cap_info.bw));  in high_freq_training()
2126 		for (j = 0; j < sdram_params->ch.cap_info.rank; j++)  in high_freq_training()
2159 	if (sdram_params->ch.cap_info.rank == 2) {  in high_freq_training()
2179 				sdram_params->ch.cap_info.rank) * -1;  in high_freq_training()
2181 			 min_val, min_val, sdram_params->ch.cap_info.rank);  in high_freq_training()
2189 				    sdram_params->ch.cap_info.rank),  in high_freq_training()
2191 				    sdram_params->ch.cap_info.rank)) * -1;  in high_freq_training()
2198 			 min_val, min_val, sdram_params->ch.cap_info.rank);  in high_freq_training()
2206 	if (sdram_params->ch.cap_info.rank == 2)  in high_freq_training()
2282 		   (cap_info->rank == 2)) {  in split_setup()
2347 	if (cap_info->rank == 2) {  in dram_all_config()
2502 		cs = cap_info->rank - 1;  in check_lp4_rzqi()
2509 		for (cs = 0; cs < cap_info->rank; cs++) {  in check_lp4_rzqi()
2689 	if (post_init != 0 && sdram_params->ch.cap_info.rank == 2) {  in sdram_init_()
2792 	cap_info->rank = cs + 1;  in dram_detect_cap()
2850 	if (cap_info->rank == 2) {  in dram_detect_cs1_row()
3396 	sdram_params_new->ch.cap_info.rank = sdram_params->ch.cap_info.rank;  in ddr_set_rate()
3721 				  (u8)sdram_params->ch.cap_info.rank);  in sdram_init()