| /rk3399_rockchip-uboot/drivers/video/tegra124/ |
| H A D | display.c | 31 int pclk = timing->pixelclock.typ; in tegra_dc_calc_refresh()
52 refresh % 1000, timing->pixelclock.typ); in print_mode()
95 timing->pixelclock.typ, shift_clock_div); in update_display_mode()
311 printf("timing->pixelclock.typ = %d\n", timing->pixelclock.typ); in dump_config()
381 plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2); in display_init()
385 } else if (plld_rate != timing->pixelclock.typ * 2) { in display_init()
387 timing->pixelclock.typ = plld_rate / 2; in display_init()
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| H A D | dp.c | 510 if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ || in tegra_dc_dp_calc_config()
514 if ((u64)timing->pixelclock.typ * link_cfg->bits_per_pixel >= in tegra_dc_dp_calc_config()
519 timing->pixelclock.typ)); in tegra_dc_dp_calc_config()
521 ratio_f = (u64)timing->pixelclock.typ * link_cfg->bits_per_pixel * f; in tegra_dc_dp_calc_config()
624 link_rate, timing->pixelclock.typ) - in tegra_dc_dp_calc_config()
640 * link_rate, timing->pixelclock.typ) - (36 / in tegra_dc_dp_calc_config()
1358 if (!timing->pixelclock.typ || !timing->hactive.typ || in tegra_dc_dp_explore_link_cfg()
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| /rk3399_rockchip-uboot/drivers/video/drm/rk628/ |
| H A D | rk628_hdmirx.c | 140 unsigned long long pixelclock, clock; in rk628_hdmirx_get_timing() local
226 pixelclock = tmds_clk; in rk628_hdmirx_get_timing()
228 pixelclock = htotal * vtotal * fps; in rk628_hdmirx_get_timing()
232 pixelclock /= 2; in rk628_hdmirx_get_timing()
235 clock = pixelclock; in rk628_hdmirx_get_timing()
251 status, hact, vact, htotal, vtotal, fps, pixelclock); in rk628_hdmirx_get_timing()
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| H A D | rk628.c | 308 ofnode_read_u32(np, "clock-frequency", &vm->pixelclock); in of_parse_rk628_display_timing()
341 dmode->clock = vm->pixelclock / 1000; in rk628_display_mode_from_videomode()
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| H A D | rk628.h | 375 u32 pixelclock; /* pixelclock in Hz */ member
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| /rk3399_rockchip-uboot/drivers/video/ |
| H A D | atmel_lcdfb.c | 141 value = get_lcdc_clk_rate(0) / timing->pixelclock.typ; in atmel_fb_init()
142 if (get_lcdc_clk_rate(0) % timing->pixelclock.typ) in atmel_fb_init()
219 timing.pixelclock.typ = panel_info.vl_clk; in lcd_ctrl_init()
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| H A D | dw_hdmi.c | 719 edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ); in dw_hdmi_enable()
723 ret = hdmi->phy_set(hdmi, edid->pixelclock.typ); in dw_hdmi_enable()
732 hdmi_audio_set_samplerate(hdmi, edid->pixelclock.typ); in dw_hdmi_enable()
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| H A D | atmel_hlcdfb.c | 326 value = priv->clk_rate / timing->pixelclock.typ; in atmel_hlcdc_init()
327 if (priv->clk_rate % timing->pixelclock.typ) in atmel_hlcdc_init()
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| H A D | tegra.c | 368 priv->pixel_clock = timing->pixelclock.typ; in tegra_lcd_ofdata_to_platdata()
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| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | drm_modes.c | 220 dmode->clock = vm->pixelclock / 1000; in drm_display_mode_from_videomode()
259 vm->pixelclock = dmode->clock * 1000; in drm_display_mode_to_videomode()
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| H A D | rockchip_dw_hdmi_qp.c | 502 hdmi_get_tmdsclock(struct rockchip_hdmi *hdmi, unsigned long pixelclock) in hdmi_get_tmdsclock() argument
504 unsigned int tmdsclock = pixelclock; in hdmi_get_tmdsclock()
511 tmdsclock = pixelclock * 2; in hdmi_get_tmdsclock()
514 tmdsclock = pixelclock * 3 / 2; in hdmi_get_tmdsclock()
517 tmdsclock = pixelclock * 5 / 4; in hdmi_get_tmdsclock()
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| H A D | rockchip_display.c | 395 int hactive, vactive, pixelclock; in rockchip_ofnode_get_display_mode() local
415 FDT_GET_INT(pixelclock, "clock-frequency"); in rockchip_ofnode_get_display_mode()
458 mode->clock = pixelclock / 1000; in rockchip_ofnode_get_display_mode()
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| /rk3399_rockchip-uboot/drivers/video/rockchip/ |
| H A D | rk3399_mipi.c | 88 priv->pix_clk = timing->pixelclock.typ; in rk_display_enable()
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| H A D | rk3288_mipi.c | 96 priv->pix_clk = timing->pixelclock.typ; in rk_mipi_enable()
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| H A D | rk_vop.c | 282 ret = clk_set_rate(&clk, timing.pixelclock.typ); in rk_display_init()
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| /rk3399_rockchip-uboot/include/ |
| H A D | drm_modes.h | 355 unsigned long pixelclock; /* pixelclock in Hz */ member
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| H A D | fdtdec.h | 924 struct timing_entry pixelclock; member
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| /rk3399_rockchip-uboot/drivers/video/sunxi/ |
| H A D | sunxi_dw_hdmi.c | 248 int div = sunxi_dw_hdmi_get_divider(edid->pixelclock.typ); in sunxi_dw_hdmi_lcdc_init()
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| H A D | sunxi_display.c | 728 timing->pixelclock.typ = mode->pixclock_khz * 1000; in sunxi_ctfb_mode_to_display_timing()
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| /rk3399_rockchip-uboot/drivers/core/ |
| H A D | ofnode.c | 472 ret |= decode_timing_property(node, "clock-frequency", &dt->pixelclock); in ofnode_decode_display_timing()
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| /rk3399_rockchip-uboot/lib/ |
| H A D | fdtdec.c | 1118 &dt->pixelclock); in fdtdec_decode_display_timing()
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| /rk3399_rockchip-uboot/common/ |
| H A D | edid.c | 1777 set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); in decode_timing()
1817 timing->pixelclock.typ, in decode_timing()
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