xref: /rk3399_rockchip-uboot/include/drm_modes.h (revision 298cc5970d24f4573ffb30717f481df2581d59b4)
1b9e63a96SMark Yao /*
2b9e63a96SMark Yao  * (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd
3b9e63a96SMark Yao  *
4b9e63a96SMark Yao  * SPDX-License-Identifier:	GPL-2.0+
5b9e63a96SMark Yao  */
6b9e63a96SMark Yao 
7b9e63a96SMark Yao #ifndef _DRM_MODES_H
8b9e63a96SMark Yao #define _DRM_MODES_H
9b9e63a96SMark Yao 
102cb51333SDamon Ding #include "fdtdec.h"
112cb51333SDamon Ding 
12ccd843b9SSandy Huang #define DRM_DISPLAY_INFO_LEN	32
13ccd843b9SSandy Huang #define DRM_CONNECTOR_NAME_LEN	32
14ccd843b9SSandy Huang #define DRM_DISPLAY_MODE_LEN	32
15ccd843b9SSandy Huang #define DRM_PROP_NAME_LEN	32
16ccd843b9SSandy Huang 
17ccd843b9SSandy Huang #define DRM_MODE_TYPE_BUILTIN	(1<<0)
18ccd843b9SSandy Huang #define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN)
19ccd843b9SSandy Huang #define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN)
20ccd843b9SSandy Huang #define DRM_MODE_TYPE_PREFERRED	(1<<3)
21ccd843b9SSandy Huang #define DRM_MODE_TYPE_DEFAULT	(1<<4)
22ccd843b9SSandy Huang #define DRM_MODE_TYPE_USERDEF	(1<<5)
23ccd843b9SSandy Huang #define DRM_MODE_TYPE_DRIVER	(1<<6)
2421016d27SAlgea Cao 
25b9e63a96SMark Yao /* Video mode flags */
26b9e63a96SMark Yao /* bit compatible with the xorg definitions. */
27b9e63a96SMark Yao #define DRM_MODE_FLAG_PHSYNC			(1 << 0)
28b9e63a96SMark Yao #define DRM_MODE_FLAG_NHSYNC			(1 << 1)
29b9e63a96SMark Yao #define DRM_MODE_FLAG_PVSYNC			(1 << 2)
30b9e63a96SMark Yao #define DRM_MODE_FLAG_NVSYNC			(1 << 3)
31b9e63a96SMark Yao #define DRM_MODE_FLAG_INTERLACE			(1 << 4)
32b9e63a96SMark Yao #define DRM_MODE_FLAG_DBLSCAN			(1 << 5)
33b9e63a96SMark Yao #define DRM_MODE_FLAG_CSYNC			(1 << 6)
34b9e63a96SMark Yao #define DRM_MODE_FLAG_PCSYNC			(1 << 7)
35b9e63a96SMark Yao #define DRM_MODE_FLAG_NCSYNC			(1 << 8)
36b9e63a96SMark Yao #define DRM_MODE_FLAG_HSKEW			(1 << 9) /* hskew provided */
37b9e63a96SMark Yao #define DRM_MODE_FLAG_BCAST			(1 << 10)
38b9e63a96SMark Yao #define DRM_MODE_FLAG_PIXMUX			(1 << 11)
39b9e63a96SMark Yao #define DRM_MODE_FLAG_DBLCLK			(1 << 12)
40b9e63a96SMark Yao #define DRM_MODE_FLAG_CLKDIV2			(1 << 13)
41e022625eSWyon Bi /*
42e022625eSWyon Bi  * When adding a new stereo mode don't forget to adjust DRM_MODE_FLAGS_3D_MAX
43e022625eSWyon Bi  * (define not exposed to user space).
44e022625eSWyon Bi  */
45e022625eSWyon Bi #define DRM_MODE_FLAG_3D_MASK			(0x1f << 14)
46e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_NONE			(0 << 14)
47e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_FRAME_PACKING		(1 << 14)
48e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE	(2 << 14)
49e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_LINE_ALTERNATIVE	(3 << 14)
50e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL	(4 << 14)
51e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_L_DEPTH		(5 << 14)
52e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH	(6 << 14)
53e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_TOP_AND_BOTTOM	(7 << 14)
54e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF	(8 << 14)
55b9e63a96SMark Yao 
56ffa55e18SShixiang Zheng /* Panel Mirror control */
57ffa55e18SShixiang Zheng #define DRM_MODE_FLAG_XMIRROR			(1<<28)
58ffa55e18SShixiang Zheng #define DRM_MODE_FLAG_YMIRROR			(1<<29)
59ffa55e18SShixiang Zheng #define DRM_MODE_FLAG_XYMIRROR			(DRM_MODE_FLAG_XMIRROR | DRM_MODE_FLAG_YMIRROR)
6094d85f7bSSandy Huang 
6194d85f7bSSandy Huang /* Picture aspect ratio options */
6294d85f7bSSandy Huang #define DRM_MODE_PICTURE_ASPECT_NONE		0
6394d85f7bSSandy Huang #define DRM_MODE_PICTURE_ASPECT_4_3		1
6494d85f7bSSandy Huang #define DRM_MODE_PICTURE_ASPECT_16_9		2
6594d85f7bSSandy Huang #define DRM_MODE_PICTURE_ASPECT_64_27		3
6694d85f7bSSandy Huang #define DRM_MODE_PICTURE_ASPECT_256_135		4
6794d85f7bSSandy Huang 
6894d85f7bSSandy Huang /* Aspect ratio flag bitmask (4 bits 22:19) */
6994d85f7bSSandy Huang #define DRM_MODE_FLAG_PIC_AR_MASK		(0x0F << 19)
7094d85f7bSSandy Huang #define  DRM_MODE_FLAG_PIC_AR_NONE \
7194d85f7bSSandy Huang 			(DRM_MODE_PICTURE_ASPECT_NONE << 19)
7294d85f7bSSandy Huang #define  DRM_MODE_FLAG_PIC_AR_4_3 \
7394d85f7bSSandy Huang 			(DRM_MODE_PICTURE_ASPECT_4_3 << 19)
7494d85f7bSSandy Huang #define  DRM_MODE_FLAG_PIC_AR_16_9 \
7594d85f7bSSandy Huang 			(DRM_MODE_PICTURE_ASPECT_16_9 << 19)
7694d85f7bSSandy Huang #define  DRM_MODE_FLAG_PIC_AR_64_27 \
7794d85f7bSSandy Huang 			(DRM_MODE_PICTURE_ASPECT_64_27 << 19)
7894d85f7bSSandy Huang #define  DRM_MODE_FLAG_PIC_AR_256_135 \
7994d85f7bSSandy Huang 			(DRM_MODE_PICTURE_ASPECT_256_135 << 19)
80ffa55e18SShixiang Zheng 
81*298cc597SDamon Ding /*
82*298cc597SDamon Ding  * DRM_MODE_ROTATE_<degrees>
83*298cc597SDamon Ding  *
84*298cc597SDamon Ding  * Signals that a drm plane is been rotated <degrees> degrees in counter
85*298cc597SDamon Ding  * clockwise direction.
86*298cc597SDamon Ding  *
87*298cc597SDamon Ding  * This define is provided as a convenience, looking up the property id
88*298cc597SDamon Ding  * using the name->prop id lookup is the preferred method.
89*298cc597SDamon Ding  */
90*298cc597SDamon Ding #define DRM_MODE_ROTATE_0       (1<<0)
91*298cc597SDamon Ding #define DRM_MODE_ROTATE_90      (1<<1)
92*298cc597SDamon Ding #define DRM_MODE_ROTATE_180     (1<<2)
93*298cc597SDamon Ding #define DRM_MODE_ROTATE_270     (1<<3)
94*298cc597SDamon Ding 
95*298cc597SDamon Ding /*
96*298cc597SDamon Ding  * DRM_MODE_ROTATE_MASK
97*298cc597SDamon Ding  *
98*298cc597SDamon Ding  * Bitmask used to look for drm plane rotations.
99*298cc597SDamon Ding  */
100*298cc597SDamon Ding #define DRM_MODE_ROTATE_MASK (\
101*298cc597SDamon Ding 		DRM_MODE_ROTATE_0  | \
102*298cc597SDamon Ding 		DRM_MODE_ROTATE_90  | \
103*298cc597SDamon Ding 		DRM_MODE_ROTATE_180 | \
104*298cc597SDamon Ding 		DRM_MODE_ROTATE_270)
105*298cc597SDamon Ding 
106*298cc597SDamon Ding /*
107*298cc597SDamon Ding  * DRM_MODE_REFLECT_<axis>
108*298cc597SDamon Ding  *
109*298cc597SDamon Ding  * Signals that the contents of a drm plane is reflected along the <axis> axis,
110*298cc597SDamon Ding  * in the same way as mirroring.
111*298cc597SDamon Ding  * See kerneldoc chapter "Plane Composition Properties" for more details.
112*298cc597SDamon Ding  *
113*298cc597SDamon Ding  * This define is provided as a convenience, looking up the property id
114*298cc597SDamon Ding  * using the name->prop id lookup is the preferred method.
115*298cc597SDamon Ding  */
116*298cc597SDamon Ding #define DRM_MODE_REFLECT_X      (1<<4)
117*298cc597SDamon Ding #define DRM_MODE_REFLECT_Y      (1<<5)
118*298cc597SDamon Ding 
119*298cc597SDamon Ding /*
120*298cc597SDamon Ding  * DRM_MODE_REFLECT_MASK
121*298cc597SDamon Ding  *
122*298cc597SDamon Ding  * Bitmask used to look for drm plane reflections.
123*298cc597SDamon Ding  */
124*298cc597SDamon Ding #define DRM_MODE_REFLECT_MASK (\
125*298cc597SDamon Ding 		DRM_MODE_REFLECT_X | \
126*298cc597SDamon Ding 		DRM_MODE_REFLECT_Y)
127*298cc597SDamon Ding 
128b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_Unknown	0
129b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_VGA		1
130b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DVII		2
131b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DVID		3
132b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DVIA		4
133b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_Composite	5
134b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_SVIDEO	6
135b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_LVDS		7
136b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_Component	8
137b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_9PinDIN	9
138b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DisplayPort	10
139b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_HDMIA	11
140b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_HDMIB	12
141b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_TV		13
142b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_eDP		14
143b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_VIRTUAL      15
144b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DSI		16
145ecc31b6eSAndy Yan #define DRM_MODE_CONNECTOR_DPI		17
146b9e63a96SMark Yao 
147b9e63a96SMark Yao #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
148b9e63a96SMark Yao #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
149b9e63a96SMark Yao #define DRM_EDID_PT_SEPARATE_SYNC  (3 << 3)
150b9e63a96SMark Yao #define DRM_EDID_PT_STEREO         (1 << 5)
151b9e63a96SMark Yao #define DRM_EDID_PT_INTERLACED     (1 << 7)
152b9e63a96SMark Yao 
15379feefb1SSandy Huang /* see also http://vektor.theorem.ca/graphics/ycbcr/ */
15479feefb1SSandy Huang enum v4l2_colorspace {
15579feefb1SSandy Huang 	/*
15679feefb1SSandy Huang 	 * Default colorspace, i.e. let the driver figure it out.
15779feefb1SSandy Huang 	 * Can only be used with video capture.
15879feefb1SSandy Huang 	 */
15979feefb1SSandy Huang 	V4L2_COLORSPACE_DEFAULT       = 0,
16079feefb1SSandy Huang 
16179feefb1SSandy Huang 	/* SMPTE 170M: used for broadcast NTSC/PAL SDTV */
16279feefb1SSandy Huang 	V4L2_COLORSPACE_SMPTE170M     = 1,
16379feefb1SSandy Huang 
16479feefb1SSandy Huang 	/* Obsolete pre-1998 SMPTE 240M HDTV standard, superseded by Rec 709 */
16579feefb1SSandy Huang 	V4L2_COLORSPACE_SMPTE240M     = 2,
16679feefb1SSandy Huang 
16779feefb1SSandy Huang 	/* Rec.709: used for HDTV */
16879feefb1SSandy Huang 	V4L2_COLORSPACE_REC709        = 3,
16979feefb1SSandy Huang 
17079feefb1SSandy Huang 	/*
17179feefb1SSandy Huang 	 * Deprecated, do not use. No driver will ever return this. This was
17279feefb1SSandy Huang 	 * based on a misunderstanding of the bt878 datasheet.
17379feefb1SSandy Huang 	 */
17479feefb1SSandy Huang 	V4L2_COLORSPACE_BT878         = 4,
17579feefb1SSandy Huang 
17679feefb1SSandy Huang 	/*
17779feefb1SSandy Huang 	 * NTSC 1953 colorspace. This only makes sense when dealing with
17879feefb1SSandy Huang 	 * really, really old NTSC recordings. Superseded by SMPTE 170M.
17979feefb1SSandy Huang 	 */
18079feefb1SSandy Huang 	V4L2_COLORSPACE_470_SYSTEM_M  = 5,
18179feefb1SSandy Huang 
18279feefb1SSandy Huang 	/*
18379feefb1SSandy Huang 	 * EBU Tech 3213 PAL/SECAM colorspace. This only makes sense when
18479feefb1SSandy Huang 	 * dealing with really old PAL/SECAM recordings. Superseded by
18579feefb1SSandy Huang 	 * SMPTE 170M.
18679feefb1SSandy Huang 	 */
18779feefb1SSandy Huang 	V4L2_COLORSPACE_470_SYSTEM_BG = 6,
18879feefb1SSandy Huang 
18979feefb1SSandy Huang 	/*
19079feefb1SSandy Huang 	 * Effectively shorthand for V4L2_COLORSPACE_SRGB, V4L2_YCBCR_ENC_601
19179feefb1SSandy Huang 	 * and V4L2_QUANTIZATION_FULL_RANGE. To be used for (Motion-)JPEG.
19279feefb1SSandy Huang 	 */
19379feefb1SSandy Huang 	V4L2_COLORSPACE_JPEG          = 7,
19479feefb1SSandy Huang 
19579feefb1SSandy Huang 	/* For RGB colorspaces such as produces by most webcams. */
19679feefb1SSandy Huang 	V4L2_COLORSPACE_SRGB          = 8,
19779feefb1SSandy Huang 
19879feefb1SSandy Huang 	/* AdobeRGB colorspace */
19979feefb1SSandy Huang 	V4L2_COLORSPACE_ADOBERGB      = 9,
20079feefb1SSandy Huang 
20179feefb1SSandy Huang 	/* BT.2020 colorspace, used for UHDTV. */
20279feefb1SSandy Huang 	V4L2_COLORSPACE_BT2020        = 10,
20379feefb1SSandy Huang 
20479feefb1SSandy Huang 	/* Raw colorspace: for RAW unprocessed images */
20579feefb1SSandy Huang 	V4L2_COLORSPACE_RAW           = 11,
20679feefb1SSandy Huang 
20779feefb1SSandy Huang 	/* DCI-P3 colorspace, used by cinema projectors */
20879feefb1SSandy Huang 	V4L2_COLORSPACE_DCI_P3        = 12,
20979feefb1SSandy Huang };
21079feefb1SSandy Huang 
211ccd843b9SSandy Huang #define CRTC_INTERLACE_HALVE_V	(1 << 0) /* halve V values for interlacing */
212ccd843b9SSandy Huang #define CRTC_STEREO_DOUBLE	(1 << 1) /* adjust timings for stereo modes */
213ccd843b9SSandy Huang #define CRTC_NO_DBLSCAN		(1 << 2) /* don't adjust doublescan */
214ccd843b9SSandy Huang #define CRTC_NO_VSCAN		(1 << 3) /* don't adjust doublescan */
2158e2bab3fSAlgea Cao #define CRTC_STEREO_DOUBLE_ONLY	(CRTC_STEREO_DOUBLE | CRTC_NO_DBLSCAN | \
2168e2bab3fSAlgea Cao 				 CRTC_NO_VSCAN)
217ccd843b9SSandy Huang 
218ccd843b9SSandy Huang #define DRM_MODE_FLAG_3D_MAX	DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
219ccd843b9SSandy Huang 
220e022625eSWyon Bi #define DRM_MODE_MATCH_TIMINGS		(1 << 0)
221e022625eSWyon Bi #define DRM_MODE_MATCH_CLOCK		(1 << 1)
222e022625eSWyon Bi #define DRM_MODE_MATCH_FLAGS		(1 << 2)
223e022625eSWyon Bi #define DRM_MODE_MATCH_3D_FLAGS		(1 << 3)
224e022625eSWyon Bi #define DRM_MODE_MATCH_ASPECT_RATIO	(1 << 4)
225e022625eSWyon Bi 
226b9e63a96SMark Yao struct drm_display_mode {
227b9e63a96SMark Yao 	/* Proposed mode values */
228b9e63a96SMark Yao 	int clock;		/* in kHz */
229b9e63a96SMark Yao 	int hdisplay;
230b9e63a96SMark Yao 	int hsync_start;
231b9e63a96SMark Yao 	int hsync_end;
232b9e63a96SMark Yao 	int htotal;
233b9e63a96SMark Yao 	int vdisplay;
234b9e63a96SMark Yao 	int vsync_start;
235b9e63a96SMark Yao 	int vsync_end;
236b9e63a96SMark Yao 	int vtotal;
237b9e63a96SMark Yao 	int vrefresh;
238b9e63a96SMark Yao 	int vscan;
239b9e63a96SMark Yao 	unsigned int flags;
24021016d27SAlgea Cao 	int picture_aspect_ratio;
241ccd843b9SSandy Huang 	int hskew;
242ccd843b9SSandy Huang 	unsigned int type;
243ccd843b9SSandy Huang 	/* Actual mode we give to hw */
244ccd843b9SSandy Huang 	int crtc_clock;         /* in KHz */
245ccd843b9SSandy Huang 	int crtc_hdisplay;
246ccd843b9SSandy Huang 	int crtc_hblank_start;
247ccd843b9SSandy Huang 	int crtc_hblank_end;
248ccd843b9SSandy Huang 	int crtc_hsync_start;
249ccd843b9SSandy Huang 	int crtc_hsync_end;
250ccd843b9SSandy Huang 	int crtc_htotal;
251ccd843b9SSandy Huang 	int crtc_hskew;
252ccd843b9SSandy Huang 	int crtc_vdisplay;
253ccd843b9SSandy Huang 	int crtc_vblank_start;
254ccd843b9SSandy Huang 	int crtc_vblank_end;
255ccd843b9SSandy Huang 	int crtc_vsync_start;
256ccd843b9SSandy Huang 	int crtc_vsync_end;
257ccd843b9SSandy Huang 	int crtc_vtotal;
2588e2bab3fSAlgea Cao 	bool invalid;
259b9e63a96SMark Yao };
260b9e63a96SMark Yao 
261a265befeSGuochun Huang /**
262a265befeSGuochun Huang  * enum drm_mode_status - hardware support status of a mode
263a265befeSGuochun Huang  * @MODE_OK: Mode OK
264a265befeSGuochun Huang  * @MODE_HSYNC: hsync out of range
265a265befeSGuochun Huang  * @MODE_VSYNC: vsync out of range
266a265befeSGuochun Huang  * @MODE_H_ILLEGAL: mode has illegal horizontal timings
267a265befeSGuochun Huang  * @MODE_V_ILLEGAL: mode has illegal vertical timings
268a265befeSGuochun Huang  * @MODE_BAD_WIDTH: requires an unsupported linepitch
269a265befeSGuochun Huang  * @MODE_NOMODE: no mode with a matching name
270a265befeSGuochun Huang  * @MODE_NO_INTERLACE: interlaced mode not supported
271a265befeSGuochun Huang  * @MODE_NO_DBLESCAN: doublescan mode not supported
272a265befeSGuochun Huang  * @MODE_NO_VSCAN: multiscan mode not supported
273a265befeSGuochun Huang  * @MODE_MEM: insufficient video memory
274a265befeSGuochun Huang  * @MODE_VIRTUAL_X: mode width too large for specified virtual size
275a265befeSGuochun Huang  * @MODE_VIRTUAL_Y: mode height too large for specified virtual size
276a265befeSGuochun Huang  * @MODE_MEM_VIRT: insufficient video memory given virtual size
277a265befeSGuochun Huang  * @MODE_NOCLOCK: no fixed clock available
278a265befeSGuochun Huang  * @MODE_CLOCK_HIGH: clock required is too high
279a265befeSGuochun Huang  * @MODE_CLOCK_LOW: clock required is too low
280a265befeSGuochun Huang  * @MODE_CLOCK_RANGE: clock/mode isn't in a ClockRange
281a265befeSGuochun Huang  * @MODE_BAD_HVALUE: horizontal timing was out of range
282a265befeSGuochun Huang  * @MODE_BAD_VVALUE: vertical timing was out of range
283a265befeSGuochun Huang  * @MODE_BAD_VSCAN: VScan value out of range
284a265befeSGuochun Huang  * @MODE_HSYNC_NARROW: horizontal sync too narrow
285a265befeSGuochun Huang  * @MODE_HSYNC_WIDE: horizontal sync too wide
286a265befeSGuochun Huang  * @MODE_HBLANK_NARROW: horizontal blanking too narrow
287a265befeSGuochun Huang  * @MODE_HBLANK_WIDE: horizontal blanking too wide
288a265befeSGuochun Huang  * @MODE_VSYNC_NARROW: vertical sync too narrow
289a265befeSGuochun Huang  * @MODE_VSYNC_WIDE: vertical sync too wide
290a265befeSGuochun Huang  * @MODE_VBLANK_NARROW: vertical blanking too narrow
291a265befeSGuochun Huang  * @MODE_VBLANK_WIDE: vertical blanking too wide
292a265befeSGuochun Huang  * @MODE_PANEL: exceeds panel dimensions
293a265befeSGuochun Huang  * @MODE_INTERLACE_WIDTH: width too large for interlaced mode
294a265befeSGuochun Huang  * @MODE_ONE_WIDTH: only one width is supported
295a265befeSGuochun Huang  * @MODE_ONE_HEIGHT: only one height is supported
296a265befeSGuochun Huang  * @MODE_ONE_SIZE: only one resolution is supported
297a265befeSGuochun Huang  * @MODE_NO_REDUCED: monitor doesn't accept reduced blanking
298a265befeSGuochun Huang  * @MODE_NO_STEREO: stereo modes not supported
299a265befeSGuochun Huang  * @MODE_NO_420: ycbcr 420 modes not supported
300a265befeSGuochun Huang  * @MODE_STALE: mode has become stale
301a265befeSGuochun Huang  * @MODE_BAD: unspecified reason
302a265befeSGuochun Huang  * @MODE_ERROR: error condition
303a265befeSGuochun Huang  *
304a265befeSGuochun Huang  * This enum is used to filter out modes not supported by the driver/hardware
305a265befeSGuochun Huang  * combination.
306a265befeSGuochun Huang  */
307a265befeSGuochun Huang enum drm_mode_status {
308a265befeSGuochun Huang 	MODE_OK = 0,
309a265befeSGuochun Huang 	MODE_HSYNC,
310a265befeSGuochun Huang 	MODE_VSYNC,
311a265befeSGuochun Huang 	MODE_H_ILLEGAL,
312a265befeSGuochun Huang 	MODE_V_ILLEGAL,
313a265befeSGuochun Huang 	MODE_BAD_WIDTH,
314a265befeSGuochun Huang 	MODE_NOMODE,
315a265befeSGuochun Huang 	MODE_NO_INTERLACE,
316a265befeSGuochun Huang 	MODE_NO_DBLESCAN,
317a265befeSGuochun Huang 	MODE_NO_VSCAN,
318a265befeSGuochun Huang 	MODE_MEM,
319a265befeSGuochun Huang 	MODE_VIRTUAL_X,
320a265befeSGuochun Huang 	MODE_VIRTUAL_Y,
321a265befeSGuochun Huang 	MODE_MEM_VIRT,
322a265befeSGuochun Huang 	MODE_NOCLOCK,
323a265befeSGuochun Huang 	MODE_CLOCK_HIGH,
324a265befeSGuochun Huang 	MODE_CLOCK_LOW,
325a265befeSGuochun Huang 	MODE_CLOCK_RANGE,
326a265befeSGuochun Huang 	MODE_BAD_HVALUE,
327a265befeSGuochun Huang 	MODE_BAD_VVALUE,
328a265befeSGuochun Huang 	MODE_BAD_VSCAN,
329a265befeSGuochun Huang 	MODE_HSYNC_NARROW,
330a265befeSGuochun Huang 	MODE_HSYNC_WIDE,
331a265befeSGuochun Huang 	MODE_HBLANK_NARROW,
332a265befeSGuochun Huang 	MODE_HBLANK_WIDE,
333a265befeSGuochun Huang 	MODE_VSYNC_NARROW,
334a265befeSGuochun Huang 	MODE_VSYNC_WIDE,
335a265befeSGuochun Huang 	MODE_VBLANK_NARROW,
336a265befeSGuochun Huang 	MODE_VBLANK_WIDE,
337a265befeSGuochun Huang 	MODE_PANEL,
338a265befeSGuochun Huang 	MODE_INTERLACE_WIDTH,
339a265befeSGuochun Huang 	MODE_ONE_WIDTH,
340a265befeSGuochun Huang 	MODE_ONE_HEIGHT,
341a265befeSGuochun Huang 	MODE_ONE_SIZE,
342a265befeSGuochun Huang 	MODE_NO_REDUCED,
343a265befeSGuochun Huang 	MODE_NO_STEREO,
344a265befeSGuochun Huang 	MODE_NO_420,
345a265befeSGuochun Huang 	MODE_STALE = -3,
346a265befeSGuochun Huang 	MODE_BAD = -2,
347a265befeSGuochun Huang 	MODE_ERROR = -1
348a265befeSGuochun Huang };
349a265befeSGuochun Huang 
3502cb51333SDamon Ding /*
3512cb51333SDamon Ding  * Subsystem independent description of a videomode.
3522cb51333SDamon Ding  * Can be generated from struct display_timing.
3532cb51333SDamon Ding  */
3542cb51333SDamon Ding struct videomode {
3552cb51333SDamon Ding 	unsigned long pixelclock;	/* pixelclock in Hz */
3562cb51333SDamon Ding 
3572cb51333SDamon Ding 	u32 hactive;
3582cb51333SDamon Ding 	u32 hfront_porch;
3592cb51333SDamon Ding 	u32 hback_porch;
3602cb51333SDamon Ding 	u32 hsync_len;
3612cb51333SDamon Ding 
3622cb51333SDamon Ding 	u32 vactive;
3632cb51333SDamon Ding 	u32 vfront_porch;
3642cb51333SDamon Ding 	u32 vback_porch;
3652cb51333SDamon Ding 	u32 vsync_len;
3662cb51333SDamon Ding 
3672cb51333SDamon Ding 	enum display_flags flags; /* display flags */
3682cb51333SDamon Ding };
3692cb51333SDamon Ding 
370e022625eSWyon Bi struct drm_display_mode *drm_mode_create(void);
371a265befeSGuochun Huang void drm_mode_copy(struct drm_display_mode *dst,
372a265befeSGuochun Huang 		   const struct drm_display_mode *src);
373e022625eSWyon Bi void drm_mode_destroy(struct drm_display_mode *mode);
374e022625eSWyon Bi bool drm_mode_match(const struct drm_display_mode *mode1,
375e022625eSWyon Bi 		    const struct drm_display_mode *mode2,
376e022625eSWyon Bi 		    unsigned int match_flags);
377e022625eSWyon Bi bool drm_mode_equal(const struct drm_display_mode *mode1,
378e022625eSWyon Bi 		    const struct drm_display_mode *mode2);
379a265befeSGuochun Huang void drm_display_mode_from_videomode(const struct videomode *vm,
380a265befeSGuochun Huang 				     struct drm_display_mode *dmode);
3812cb51333SDamon Ding void drm_display_mode_to_videomode(const struct drm_display_mode *dmode,
3822cb51333SDamon Ding 				   struct videomode *vm);
383e022625eSWyon Bi 
384b9e63a96SMark Yao #endif
385