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Searched refs:phy (Results 1 – 25 of 493) sorted by relevance

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/rk3399_rockchip-uboot/include/
H A Dgeneric-phy.h58 struct phy { struct
89 int (*of_xlate)(struct phy *phy, struct ofnode_phandle_args *args);
103 int (*init)(struct phy *phy);
118 int (*exit)(struct phy *phy);
130 int (*reset)(struct phy *phy);
142 int (*configure)(struct phy *phy, union phy_configure_opts *opts);
160 int (*validate)(struct phy *phy, enum phy_mode mode, int submode,
175 int (*power_on)(struct phy *phy);
189 int (*power_off)(struct phy *phy);
191 int (*set_mode)(struct phy *phy, enum phy_mode mode, int submode);
[all …]
/rk3399_rockchip-uboot/drivers/video/drm/
H A Drockchip_phy.c10 int rockchip_phy_init(struct rockchip_phy *phy) in rockchip_phy_init() argument
12 if (!phy) in rockchip_phy_init()
15 if (phy->funcs && phy->funcs->init) in rockchip_phy_init()
16 return phy->funcs->init(phy); in rockchip_phy_init()
21 int rockchip_phy_power_on(struct rockchip_phy *phy) in rockchip_phy_power_on() argument
23 if (!phy) in rockchip_phy_power_on()
26 if (phy->funcs && phy->funcs->power_on) in rockchip_phy_power_on()
27 return phy->funcs->power_on(phy); in rockchip_phy_power_on()
32 int rockchip_phy_power_off(struct rockchip_phy *phy) in rockchip_phy_power_off() argument
34 if (!phy) in rockchip_phy_power_off()
[all …]
H A Drockchip_phy.h20 int (*init)(struct rockchip_phy *phy);
21 int (*power_on)(struct rockchip_phy *phy);
22 int (*power_off)(struct rockchip_phy *phy);
23 unsigned long (*set_pll)(struct rockchip_phy *phy, unsigned long rate);
24 int (*set_bus_width)(struct rockchip_phy *phy, u32 bus_width);
25 long (*round_rate)(struct rockchip_phy *phy, unsigned long rate);
26 int (*set_mode)(struct rockchip_phy *phy, enum phy_mode mode);
36 int rockchip_phy_init(struct rockchip_phy *phy);
37 int rockchip_phy_power_off(struct rockchip_phy *phy);
38 int rockchip_phy_power_on(struct rockchip_phy *phy);
[all …]
H A Dinno_video_phy.c118 static int inno_video_phy_power_on(struct rockchip_phy *phy) in inno_video_phy_power_on() argument
120 struct inno_video_phy *inno = dev_get_priv(phy->dev); in inno_video_phy_power_on()
150 dev_err(phy->dev, "PLL is not lock\n"); in inno_video_phy_power_on()
159 static int inno_video_phy_power_off(struct rockchip_phy *phy) in inno_video_phy_power_off() argument
161 struct inno_video_phy *inno = dev_get_priv(phy->dev); in inno_video_phy_power_off()
169 static int inno_video_phy_set_mode(struct rockchip_phy *phy, in inno_video_phy_set_mode() argument
172 struct inno_video_phy *inno = dev_get_priv(phy->dev); in inno_video_phy_set_mode()
187 inno_video_phy_set_bus_width(struct rockchip_phy *phy, u32 bus_width) in inno_video_phy_set_bus_width() argument
189 struct inno_video_phy *inno = dev_get_priv(phy->dev); in inno_video_phy_set_bus_width()
206 struct rockchip_phy *phy = in inno_video_phy_probe() local
[all …]
/rk3399_rockchip-uboot/drivers/phy/
H A Dphy-uclass.c44 static struct phy_counts *phy_get_counts(struct phy *phy) in phy_get_counts() argument
49 if (!generic_phy_valid(phy)) in phy_get_counts()
52 uc_priv = dev_get_uclass_priv(phy->dev); in phy_get_counts()
54 if (counts->id == phy->id) in phy_get_counts()
60 static int phy_alloc_counts(struct phy *phy) in phy_alloc_counts() argument
65 if (!generic_phy_valid(phy)) in phy_alloc_counts()
67 if (phy_get_counts(phy)) in phy_alloc_counts()
70 uc_priv = dev_get_uclass_priv(phy->dev); in phy_alloc_counts()
75 counts->id = phy->id; in phy_alloc_counts()
103 static int generic_phy_xlate_offs_flags(struct phy *phy, in generic_phy_xlate_offs_flags() argument
[all …]
H A DMakefile8 obj-$(CONFIG_$(SPL_)PHY) += phy-uclass.o
9 obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o
10 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
11 obj-$(CONFIG_PHY_ROCKCHIP_NANENG_USB2) += phy-rockchip-naneng-usb2.o
12 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB3) += phy-rockchip-inno-usb3.o
13 obj-$(CONFIG_PHY_ROCKCHIP_NANENG_EDP) += phy-rockchip-naneng-edp.o
14 obj-$(CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX) += phy-rockchip-samsung-hdptx.o
15 obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
16 obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
17 obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o
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H A Dsandbox-phy.c20 static int sandbox_phy_power_on(struct phy *phy) in sandbox_phy_power_on() argument
22 struct sandbox_phy_priv *priv = dev_get_priv(phy->dev); in sandbox_phy_power_on()
35 static int sandbox_phy_power_off(struct phy *phy) in sandbox_phy_power_off() argument
37 struct sandbox_phy_priv *priv = dev_get_priv(phy->dev); in sandbox_phy_power_off()
49 if (phy->id) in sandbox_phy_power_off()
57 static int sandbox_phy_init(struct phy *phy) in sandbox_phy_init() argument
59 struct sandbox_phy_priv *priv = dev_get_priv(phy->dev); in sandbox_phy_init()
67 static int sandbox_phy_exit(struct phy *phy) in sandbox_phy_exit() argument
69 struct sandbox_phy_priv *priv = dev_get_priv(phy->dev); in sandbox_phy_exit()
H A Dsti_usb_phy.c44 static int sti_usb_phy_deassert(struct sti_usb_phy *phy) in sti_usb_phy_deassert() argument
48 ret = reset_deassert(&phy->global_ctl); in sti_usb_phy_deassert()
54 ret = reset_deassert(&phy->port_ctl); in sti_usb_phy_deassert()
61 static int sti_usb_phy_init(struct phy *usb_phy) in sti_usb_phy_init()
64 struct sti_usb_phy *phy = dev_get_priv(dev); in sti_usb_phy_init() local
68 reg = (void __iomem *)phy->regmap->base + phy->ctrl; in sti_usb_phy_init()
73 reg = (void __iomem *)phy->regmap->base + phy->param; in sti_usb_phy_init()
77 return sti_usb_phy_deassert(phy); in sti_usb_phy_init()
80 static int sti_usb_phy_exit(struct phy *usb_phy) in sti_usb_phy_exit()
83 struct sti_usb_phy *phy = dev_get_priv(dev); in sti_usb_phy_exit() local
[all …]
H A Dphy-rockchip-naneng-usb2.c266 static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy) in rockchip_usb2phy_check_vbus() argument
268 struct udevice *parent = phy->dev->parent; in rockchip_usb2phy_check_vbus()
275 if (phy->id == USB2PHY_PORT_HOST) { in rockchip_usb2phy_check_vbus()
277 } else if (phy->id == USB2PHY_PORT_OTG) { in rockchip_usb2phy_check_vbus()
289 static int rockchip_usb2phy_init(struct phy *phy) in rockchip_usb2phy_init() argument
291 struct udevice *parent = phy->dev->parent; in rockchip_usb2phy_init()
295 if (phy->id == USB2PHY_PORT_OTG) { in rockchip_usb2phy_init()
297 } else if (phy->id == USB2PHY_PORT_HOST) { in rockchip_usb2phy_init()
300 dev_err(phy->dev, "phy id %lu not support", phy->id); in rockchip_usb2phy_init()
312 static int rockchip_usb2phy_exit(struct phy *phy) in rockchip_usb2phy_exit() argument
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Dusb_phy.c117 __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, in usb_phy_write() argument
128 usbc_bit = 1 << (phy->id * 2); in usb_phy_write()
150 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) in sunxi_usb_phy_config() argument
153 if (phy->id == 0) in sunxi_usb_phy_config()
156 clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02); in sunxi_usb_phy_config()
159 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) in sunxi_usb_phy_config() argument
163 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) in sunxi_usb_phy_config() argument
170 if (phy->id == 0) in sunxi_usb_phy_config()
171 usb_phy_write(phy, 0x0c, 0x01, 1); in sunxi_usb_phy_config()
174 usb_phy_write(phy, 0x20, 0x14, 5); in sunxi_usb_phy_config()
[all …]
/rk3399_rockchip-uboot/drivers/video/sunxi/
H A Dsunxi_dw_hdmi.c59 struct sunxi_hdmi_phy * const phy = in sunxi_dw_hdmi_phy_init() local
68 writel(0, &phy->ctrl); in sunxi_dw_hdmi_phy_init()
69 setbits_le32(&phy->ctrl, BIT(0)); in sunxi_dw_hdmi_phy_init()
71 setbits_le32(&phy->ctrl, BIT(16)); in sunxi_dw_hdmi_phy_init()
72 setbits_le32(&phy->ctrl, BIT(1)); in sunxi_dw_hdmi_phy_init()
74 setbits_le32(&phy->ctrl, BIT(2)); in sunxi_dw_hdmi_phy_init()
76 setbits_le32(&phy->ctrl, BIT(3)); in sunxi_dw_hdmi_phy_init()
78 setbits_le32(&phy->ctrl, BIT(19)); in sunxi_dw_hdmi_phy_init()
80 setbits_le32(&phy->ctrl, BIT(18)); in sunxi_dw_hdmi_phy_init()
81 setbits_le32(&phy->ctrl, 7 << 4); in sunxi_dw_hdmi_phy_init()
[all …]
/rk3399_rockchip-uboot/drivers/usb/dwc3/
H A Dti_usb_phy.c117 static struct usb3_dpll_params *ti_usb3_get_dpll_params(struct ti_usb_phy *phy) in ti_usb3_get_dpll_params() argument
120 struct usb3_dpll_map *dpll_map = phy->dpll_map; in ti_usb3_get_dpll_params()
129 dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate); in ti_usb3_get_dpll_params()
134 static int ti_usb3_dpll_wait_lock(struct ti_usb_phy *phy) in ti_usb3_dpll_wait_lock() argument
138 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_STATUS); in ti_usb3_dpll_wait_lock()
146 static int ti_usb3_dpll_program(struct ti_usb_phy *phy) in ti_usb3_dpll_program() argument
151 if (!phy->pll_ctrl_base) in ti_usb3_dpll_program()
154 dpll_params = ti_usb3_get_dpll_params(phy); in ti_usb3_dpll_program()
158 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); in ti_usb3_dpll_program()
161 ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); in ti_usb3_dpll_program()
[all …]
H A Dsamsung_usb_phy.c15 void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy) in exynos5_usb3_phy_init() argument
20 writel(0x0, &phy->phy_reg0); in exynos5_usb3_phy_init()
22 clrbits_le32(&phy->phy_param0, in exynos5_usb3_phy_init()
27 setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL); in exynos5_usb3_phy_init()
30 writel(0x0, &phy->phy_resume); in exynos5_usb3_phy_init()
36 setbits_le32(&phy->link_system, in exynos5_usb3_phy_init()
41 clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK); in exynos5_usb3_phy_init()
42 setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH); in exynos5_usb3_phy_init()
44 setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL); in exynos5_usb3_phy_init()
47 clrbits_le32(&phy->phy_test, in exynos5_usb3_phy_init()
[all …]
/rk3399_rockchip-uboot/drivers/usb/gadget/
H A Ddwc2_udc_otg_phy.c43 struct dwc2_usbotg_phy *phy = in otg_phy_init() local
55 writel((readl(&phy->phypwr) in otg_phy_init()
57 &~FORCE_SUSPEND_0), &phy->phypwr); in otg_phy_init()
59 writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN) in otg_phy_init()
60 &~FORCE_SUSPEND_0), &phy->phypwr); in otg_phy_init()
63 writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 | in otg_phy_init()
65 &phy->phyclk); /* PLL 24Mhz */ in otg_phy_init()
67 writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) | in otg_phy_init()
68 CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */ in otg_phy_init()
70 writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST)) in otg_phy_init()
[all …]
/rk3399_rockchip-uboot/board/highbank/
H A Dahci.c42 static u32 __combo_phy_reg_read(u8 phy, u8 dev, u32 addr) in __combo_phy_reg_read() argument
45 writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy); in __combo_phy_reg_read()
46 data = readl(CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr)); in __combo_phy_reg_read()
50 static void __combo_phy_reg_write(u8 phy, u8 dev, u32 addr, u32 data) in __combo_phy_reg_write() argument
52 writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy); in __combo_phy_reg_write()
53 writel(data, CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr)); in __combo_phy_reg_write()
56 static u32 combo_phy_read(u8 phy, u32 addr) in combo_phy_read() argument
59 if (phy == 5) in combo_phy_read()
61 while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) in combo_phy_read()
63 __combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr); in combo_phy_read()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Dpipe3-phy.c86 static int omap_pipe3_wait_lock(struct omap_pipe3 *phy) in omap_pipe3_wait_lock() argument
93 val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); in omap_pipe3_wait_lock()
106 static int omap_pipe3_dpll_program(struct omap_pipe3 *phy) in omap_pipe3_dpll_program() argument
111 dpll_params = omap_pipe3_get_dpll_params(phy); in omap_pipe3_dpll_program()
117 val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); in omap_pipe3_dpll_program()
120 omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); in omap_pipe3_dpll_program()
122 val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); in omap_pipe3_dpll_program()
125 omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); in omap_pipe3_dpll_program()
127 val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); in omap_pipe3_dpll_program()
130 omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); in omap_pipe3_dpll_program()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A Dxusb-padctl-common.c16 int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy) in tegra_xusb_phy_prepare() argument
18 if (phy && phy->ops && phy->ops->prepare) in tegra_xusb_phy_prepare()
19 return phy->ops->prepare(phy); in tegra_xusb_phy_prepare()
21 return phy ? -ENOSYS : -EINVAL; in tegra_xusb_phy_prepare()
24 int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy) in tegra_xusb_phy_enable() argument
26 if (phy && phy->ops && phy->ops->enable) in tegra_xusb_phy_enable()
27 return phy->ops->enable(phy); in tegra_xusb_phy_enable()
29 return phy ? -ENOSYS : -EINVAL; in tegra_xusb_phy_enable()
32 int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy) in tegra_xusb_phy_disable() argument
34 if (phy && phy->ops && phy->ops->disable) in tegra_xusb_phy_disable()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-aspeed/ast2500/
H A Dsdram_ast2500.c64 u32 phy[117]; member
72 struct ast2500_ddr_phy *phy; member
76 static int ast2500_sdrammc_init_phy(struct ast2500_ddr_phy *phy) in ast2500_sdrammc_init_phy() argument
78 writel(0, &phy->phy[2]); in ast2500_sdrammc_init_phy()
79 writel(0, &phy->phy[6]); in ast2500_sdrammc_init_phy()
80 writel(0, &phy->phy[8]); in ast2500_sdrammc_init_phy()
81 writel(0, &phy->phy[10]); in ast2500_sdrammc_init_phy()
82 writel(0, &phy->phy[12]); in ast2500_sdrammc_init_phy()
83 writel(0, &phy->phy[42]); in ast2500_sdrammc_init_phy()
84 writel(0, &phy->phy[44]); in ast2500_sdrammc_init_phy()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/dram/
H A Dcmd_ddrmphy.c35 } phy[UNIPHIER_MAX_NR_DDRMPHY]; member
42 .phy = {
51 .phy = {
73 int phy, dx; in dump_loop() local
75 for (phy = 0; phy < param->nr_phy; phy++) { in dump_loop()
76 phy_base = ioremap(param->phy[phy].base, SZ_4K); in dump_loop()
79 for (dx = 0; dx < param->phy[phy].nr_dx; dx++) { in dump_loop()
80 printf("PHY%dDX%d:", phy, dx); in dump_loop()
94 int phy, zq, i; in zq_dump() local
99 for (phy = 0; phy < param->nr_phy; phy++) { in zq_dump()
[all …]
H A Dcmd_ddrphy.c35 } phy[UNIPHIER_MAX_NR_DDRPHY]; member
42 .phy = {
50 .phy = {
60 .phy = {
68 .phy = {
88 int phy, dx; in dump_loop() local
90 for (phy = 0; phy < param->nr_phy; phy++) { in dump_loop()
91 phy_base = ioremap(param->phy[phy].base, SZ_4K); in dump_loop()
94 for (dx = 0; dx < param->phy[phy].nr_dx; dx++) { in dump_loop()
95 printf("PHY%dDX%d:", phy, dx); in dump_loop()
[all …]
/rk3399_rockchip-uboot/drivers/usb/host/
H A Dxhci-exynos5.c94 static void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy) in exynos5_usb3_phy_init() argument
102 writel(0x0, &phy->phy_reg0); in exynos5_usb3_phy_init()
104 clrbits_le32(&phy->phy_param0, in exynos5_usb3_phy_init()
109 setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL); in exynos5_usb3_phy_init()
111 writel(0x0, &phy->phy_resume); in exynos5_usb3_phy_init()
117 setbits_le32(&phy->link_system, in exynos5_usb3_phy_init()
122 clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK); in exynos5_usb3_phy_init()
123 setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH); in exynos5_usb3_phy_init()
125 setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL); in exynos5_usb3_phy_init()
128 clrbits_le32(&phy->phy_test, in exynos5_usb3_phy_init()
[all …]
H A Dxhci-keystone.c41 struct keystone_xhci_phy *phy; member
46 static void keystone_xhci_phy_set(struct keystone_xhci_phy *phy) in keystone_xhci_phy_set() argument
55 val = readl(&phy->phy_clock); in keystone_xhci_phy_set()
58 writel(val, &phy->phy_clock); in keystone_xhci_phy_set()
61 static void keystone_xhci_phy_unset(struct keystone_xhci_phy *phy) in keystone_xhci_phy_unset() argument
66 val = readl(&phy->phy_clock); in keystone_xhci_phy_unset()
68 writel(val, &phy->phy_clock); in keystone_xhci_phy_unset()
95 struct keystone_xhci_phy *phy; in xhci_hcd_init() local
98 phy = (struct keystone_xhci_phy *)CONFIG_DEV_USB_PHY_BASE; in xhci_hcd_init()
101 val = readl(&(phy->phy_clock)); in xhci_hcd_init()
[all …]
/rk3399_rockchip-uboot/board/varisys/cyrus/
H A Deth.c32 static void cyrus_phy_tuning(int phy) in cyrus_phy_tuning() argument
37 printf("Tuning PHY @ %d\n", phy); in cyrus_phy_tuning()
40 miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8104); in cyrus_phy_tuning()
42 miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0xf0f0); in cyrus_phy_tuning()
44 miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8105); in cyrus_phy_tuning()
46 miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000); in cyrus_phy_tuning()
48 miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8106); in cyrus_phy_tuning()
50 miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000); in cyrus_phy_tuning()
52 miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0x0, 0x1340); in cyrus_phy_tuning()
/rk3399_rockchip-uboot/doc/device-tree-bindings/net/
H A Daltera_tse.txt22 - phy-mode: See ethernet.txt in the same directory.
23 - phy-handle: See ethernet.txt in the same directory.
24 - phy-addr: See ethernet.txt in the same directory. A configuration should
25 include phy-handle or phy-addr.
33 - mdio device tree subnode: When the TSE has a phy connected to its local
41 For each phy on the mdio bus, there must be a node with the following
44 - reg: phy id used to communicate to phy.
45 - device_type: Must be "ethernet-phy".
70 phy-mode = "gmii";
73 phy-handle = <&phy0>;
[all …]
/rk3399_rockchip-uboot/board/freescale/p2041rdb/
H A Deth.c83 char phy[16]; in board_ft_fman_fixup_port() local
87 sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1); in board_ft_fman_fixup_port()
88 fdt_set_phy_handle(fdt, compat, addr, phy); in board_ft_fman_fixup_port()
99 sprintf(phy, "phy_sgmii_%x", in board_ft_fman_fixup_port()
102 fdt_set_phy_handle(fdt, compat, addr, phy); in board_ft_fman_fixup_port()
104 sprintf(phy, "phy_sgmii_%x", in board_ft_fman_fixup_port()
107 fdt_set_phy_handle(fdt, compat, addr, phy); in board_ft_fman_fixup_port()
116 sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); in board_ft_fman_fixup_port()
117 fdt_set_phy_handle(fdt, compat, addr, phy); in board_ft_fman_fixup_port()

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