Lines Matching refs:phy
59 struct sunxi_hdmi_phy * const phy = in sunxi_dw_hdmi_phy_init() local
68 writel(0, &phy->ctrl); in sunxi_dw_hdmi_phy_init()
69 setbits_le32(&phy->ctrl, BIT(0)); in sunxi_dw_hdmi_phy_init()
71 setbits_le32(&phy->ctrl, BIT(16)); in sunxi_dw_hdmi_phy_init()
72 setbits_le32(&phy->ctrl, BIT(1)); in sunxi_dw_hdmi_phy_init()
74 setbits_le32(&phy->ctrl, BIT(2)); in sunxi_dw_hdmi_phy_init()
76 setbits_le32(&phy->ctrl, BIT(3)); in sunxi_dw_hdmi_phy_init()
78 setbits_le32(&phy->ctrl, BIT(19)); in sunxi_dw_hdmi_phy_init()
80 setbits_le32(&phy->ctrl, BIT(18)); in sunxi_dw_hdmi_phy_init()
81 setbits_le32(&phy->ctrl, 7 << 4); in sunxi_dw_hdmi_phy_init()
85 while ((readl(&phy->status) & 0x80) == 0) { in sunxi_dw_hdmi_phy_init()
92 setbits_le32(&phy->ctrl, 0xf << 8); in sunxi_dw_hdmi_phy_init()
93 setbits_le32(&phy->ctrl, BIT(7)); in sunxi_dw_hdmi_phy_init()
95 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_init()
96 writel(0x80084343, &phy->clk); in sunxi_dw_hdmi_phy_init()
98 writel(1, &phy->unk3); in sunxi_dw_hdmi_phy_init()
99 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_init()
101 tmp = (readl(&phy->status) & 0x1f800) >> 11; in sunxi_dw_hdmi_phy_init()
102 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_init()
103 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_init()
104 writel(0x01FF0F7F, &phy->ctrl); in sunxi_dw_hdmi_phy_init()
105 writel(0x80639000, &phy->unk1); in sunxi_dw_hdmi_phy_init()
106 writel(0x0F81C405, &phy->unk2); in sunxi_dw_hdmi_phy_init()
109 writel(0x54524545, &phy->read_en); in sunxi_dw_hdmi_phy_init()
111 writel(0x42494E47, &phy->unscramble); in sunxi_dw_hdmi_phy_init()
116 struct sunxi_hdmi_phy * const phy = in sunxi_dw_hdmi_get_plug_in_status() local
119 return !!(readl(&phy->status) & (1 << 19)); in sunxi_dw_hdmi_get_plug_in_status()
138 struct sunxi_hdmi_phy * const phy = in sunxi_dw_hdmi_phy_set() local
149 writel(0x30dc5fc0, &phy->pll); in sunxi_dw_hdmi_phy_set()
150 writel(0x800863C0, &phy->clk); in sunxi_dw_hdmi_phy_set()
152 writel(0x00000001, &phy->unk3); in sunxi_dw_hdmi_phy_set()
153 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
155 tmp = (readl(&phy->status) & 0x1f800) >> 11; in sunxi_dw_hdmi_phy_set()
156 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
158 setbits_le32(&phy->pll, tmp + 2); in sunxi_dw_hdmi_phy_set()
160 setbits_le32(&phy->pll, 0x3f); in sunxi_dw_hdmi_phy_set()
162 writel(0x01FFFF7F, &phy->ctrl); in sunxi_dw_hdmi_phy_set()
163 writel(0x8063b000, &phy->unk1); in sunxi_dw_hdmi_phy_set()
164 writel(0x0F8246B5, &phy->unk2); in sunxi_dw_hdmi_phy_set()
167 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
168 writel(0x80084381, &phy->clk); in sunxi_dw_hdmi_phy_set()
170 writel(0x00000001, &phy->unk3); in sunxi_dw_hdmi_phy_set()
171 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
173 tmp = (readl(&phy->status) & 0x1f800) >> 11; in sunxi_dw_hdmi_phy_set()
174 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
175 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
176 writel(0x01FFFF7F, &phy->ctrl); in sunxi_dw_hdmi_phy_set()
177 writel(0x8063a800, &phy->unk1); in sunxi_dw_hdmi_phy_set()
178 writel(0x0F81C485, &phy->unk2); in sunxi_dw_hdmi_phy_set()
181 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
182 writel(0x80084343, &phy->clk); in sunxi_dw_hdmi_phy_set()
184 writel(0x00000001, &phy->unk3); in sunxi_dw_hdmi_phy_set()
185 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
187 tmp = (readl(&phy->status) & 0x1f800) >> 11; in sunxi_dw_hdmi_phy_set()
188 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
189 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
190 writel(0x01FFFF7F, &phy->ctrl); in sunxi_dw_hdmi_phy_set()
191 writel(0x8063b000, &phy->unk1); in sunxi_dw_hdmi_phy_set()
192 writel(0x0F81C405, &phy->unk2); in sunxi_dw_hdmi_phy_set()
195 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
196 writel(0x8008430a, &phy->clk); in sunxi_dw_hdmi_phy_set()
198 writel(0x00000001, &phy->unk3); in sunxi_dw_hdmi_phy_set()
199 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
201 tmp = (readl(&phy->status) & 0x1f800) >> 11; in sunxi_dw_hdmi_phy_set()
202 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
203 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
204 writel(0x01FFFF7F, &phy->ctrl); in sunxi_dw_hdmi_phy_set()
205 writel(0x8063b000, &phy->unk1); in sunxi_dw_hdmi_phy_set()
206 writel(0x0F81C405, &phy->unk2); in sunxi_dw_hdmi_phy_set()
296 struct sunxi_hdmi_phy * const phy = in sunxi_dw_hdmi_enable() local
314 setbits_le32(&phy->pol, 0x300); in sunxi_dw_hdmi_enable()
317 setbits_le32(&phy->ctrl, 0xf << 12); in sunxi_dw_hdmi_enable()
325 writel(0, &phy->unscramble); in sunxi_dw_hdmi_enable()