1*a272c99dSLukasz Majewski /**
2*a272c99dSLukasz Majewski * samsung_usb_phy.c - DesignWare USB3 (DWC3) PHY handling file
3*a272c99dSLukasz Majewski *
4*a272c99dSLukasz Majewski * Copyright (C) 2015 Samsung Electronics
5*a272c99dSLukasz Majewski *
6*a272c99dSLukasz Majewski * Author: Joonyoung Shim <jy0922.shim@samsung.com>
7*a272c99dSLukasz Majewski *
8*a272c99dSLukasz Majewski * SPDX-License-Identifier: GPL-2.0
9*a272c99dSLukasz Majewski */
10*a272c99dSLukasz Majewski
11*a272c99dSLukasz Majewski #include <common.h>
12*a272c99dSLukasz Majewski #include <asm/arch/power.h>
13*a272c99dSLukasz Majewski #include <asm/arch/xhci-exynos.h>
14*a272c99dSLukasz Majewski
exynos5_usb3_phy_init(struct exynos_usb3_phy * phy)15*a272c99dSLukasz Majewski void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy)
16*a272c99dSLukasz Majewski {
17*a272c99dSLukasz Majewski u32 reg;
18*a272c99dSLukasz Majewski
19*a272c99dSLukasz Majewski /* Reset USB 3.0 PHY */
20*a272c99dSLukasz Majewski writel(0x0, &phy->phy_reg0);
21*a272c99dSLukasz Majewski
22*a272c99dSLukasz Majewski clrbits_le32(&phy->phy_param0,
23*a272c99dSLukasz Majewski /* Select PHY CLK source */
24*a272c99dSLukasz Majewski PHYPARAM0_REF_USE_PAD |
25*a272c99dSLukasz Majewski /* Set Loss-of-Signal Detector sensitivity */
26*a272c99dSLukasz Majewski PHYPARAM0_REF_LOSLEVEL_MASK);
27*a272c99dSLukasz Majewski setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL);
28*a272c99dSLukasz Majewski
29*a272c99dSLukasz Majewski
30*a272c99dSLukasz Majewski writel(0x0, &phy->phy_resume);
31*a272c99dSLukasz Majewski
32*a272c99dSLukasz Majewski /*
33*a272c99dSLukasz Majewski * Setting the Frame length Adj value[6:1] to default 0x20
34*a272c99dSLukasz Majewski * See xHCI 1.0 spec, 5.2.4
35*a272c99dSLukasz Majewski */
36*a272c99dSLukasz Majewski setbits_le32(&phy->link_system,
37*a272c99dSLukasz Majewski LINKSYSTEM_XHCI_VERSION_CONTROL |
38*a272c99dSLukasz Majewski LINKSYSTEM_FLADJ(0x20));
39*a272c99dSLukasz Majewski
40*a272c99dSLukasz Majewski /* Set Tx De-Emphasis level */
41*a272c99dSLukasz Majewski clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK);
42*a272c99dSLukasz Majewski setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH);
43*a272c99dSLukasz Majewski
44*a272c99dSLukasz Majewski setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL);
45*a272c99dSLukasz Majewski
46*a272c99dSLukasz Majewski /* PHYTEST POWERDOWN Control */
47*a272c99dSLukasz Majewski clrbits_le32(&phy->phy_test,
48*a272c99dSLukasz Majewski PHYTEST_POWERDOWN_SSP |
49*a272c99dSLukasz Majewski PHYTEST_POWERDOWN_HSP);
50*a272c99dSLukasz Majewski
51*a272c99dSLukasz Majewski /* UTMI Power Control */
52*a272c99dSLukasz Majewski writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi);
53*a272c99dSLukasz Majewski
54*a272c99dSLukasz Majewski /* Use core clock from main PLL */
55*a272c99dSLukasz Majewski reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
56*a272c99dSLukasz Majewski /* Default 24Mhz crystal clock */
57*a272c99dSLukasz Majewski PHYCLKRST_FSEL(FSEL_CLKSEL_24M) |
58*a272c99dSLukasz Majewski PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
59*a272c99dSLukasz Majewski PHYCLKRST_SSC_REFCLKSEL(0) |
60*a272c99dSLukasz Majewski /* Force PortReset of PHY */
61*a272c99dSLukasz Majewski PHYCLKRST_PORTRESET |
62*a272c99dSLukasz Majewski /* Digital power supply in normal operating mode */
63*a272c99dSLukasz Majewski PHYCLKRST_RETENABLEN |
64*a272c99dSLukasz Majewski /* Enable ref clock for SS function */
65*a272c99dSLukasz Majewski PHYCLKRST_REF_SSP_EN |
66*a272c99dSLukasz Majewski /* Enable spread spectrum */
67*a272c99dSLukasz Majewski PHYCLKRST_SSC_EN |
68*a272c99dSLukasz Majewski /* Power down HS Bias and PLL blocks in suspend mode */
69*a272c99dSLukasz Majewski PHYCLKRST_COMMONONN;
70*a272c99dSLukasz Majewski
71*a272c99dSLukasz Majewski writel(reg, &phy->phy_clk_rst);
72*a272c99dSLukasz Majewski
73*a272c99dSLukasz Majewski /* giving time to Phy clock to settle before resetting */
74*a272c99dSLukasz Majewski udelay(10);
75*a272c99dSLukasz Majewski
76*a272c99dSLukasz Majewski reg &= ~PHYCLKRST_PORTRESET;
77*a272c99dSLukasz Majewski writel(reg, &phy->phy_clk_rst);
78*a272c99dSLukasz Majewski }
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