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Searched refs:pctl (Results 1 – 25 of 36) sorted by relevance

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/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_rk322x.c27 struct rk322x_ddr_pctl *pctl; member
153 static void send_command(struct rk322x_ddr_pctl *pctl, in send_command() argument
156 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
158 while (readl(&pctl->mcmd) & START_CMD) in send_command()
165 struct rk322x_ddr_pctl *pctl = chan->pctl; in memory_init() local
169 send_command(pctl, 3, DESELECT_CMD, 0); in memory_init()
171 send_command(pctl, 3, PREA_CMD, 0); in memory_init()
172 send_command(pctl, 3, MRS_CMD, in memory_init()
177 send_command(pctl, 3, MRS_CMD, in memory_init()
182 send_command(pctl, 3, MRS_CMD, in memory_init()
[all …]
H A Ddmc-rk3368.c30 struct rk3368_ddr_pctl *pctl; member
195 static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd) in send_command() argument
200 writel(mcmd, &pctl->mcmd); in send_command()
201 while (readl(&pctl->mcmd) & START_CMD) in send_command()
205 static void send_mrs(struct rk3368_ddr_pctl *pctl, in send_mrs() argument
211 writel(mcmd, &pctl->mcmd); in send_mrs()
212 while (readl(&pctl->mcmd) & START_CMD) in send_mrs()
216 static int memory_init(struct rk3368_ddr_pctl *pctl, in memory_init() argument
228 writel(POWER_UP_START, &pctl->powctl); in memory_init()
237 } while (!(readl(&pctl->powstat) & POWER_UP_DONE)); in memory_init()
[all …]
H A Dsdram_rk3288.c33 struct rk3288_ddr_pctl *pctl; member
174 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) in dfi_cfg() argument
176 writel(DFI_INIT_START, &pctl->dfistcfg0); in dfi_cfg()
178 &pctl->dfistcfg1); in dfi_cfg()
179 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); in dfi_cfg()
181 &pctl->dfilpcfg0); in dfi_cfg()
183 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); in dfi_cfg()
184 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); in dfi_cfg()
185 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); in dfi_cfg()
186 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); in dfi_cfg()
[all …]
H A Dsdram_rv1108_pctl_phy.c106 &priv->pctl->mcmd); in send_command()
107 while (readl(&priv->pctl->mcmd) & START_CMD) in send_command()
201 state = readl(&priv->pctl->stat) & PCTL_CTL_STAT_MASK; in move_to_config_state()
204 writel(WAKEUP_STATE, &priv->pctl->sctl); in move_to_config_state()
205 while ((readl(&priv->pctl->stat) & PCTL_CTL_STAT_MASK) in move_to_config_state()
214 writel(CFG_STATE, &priv->pctl->sctl); in move_to_config_state()
215 while ((readl(&priv->pctl->stat) & PCTL_CTL_STAT_MASK) in move_to_config_state()
232 state = readl(&priv->pctl->stat) & PCTL_CTL_STAT_MASK; in move_to_access_state()
235 writel(WAKEUP_STATE, &priv->pctl->sctl); in move_to_access_state()
236 while ((readl(&priv->pctl->stat) & in move_to_access_state()
[all …]
H A Dsdram_rk3188.c31 struct rk3288_ddr_pctl *pctl; member
175 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) in dfi_cfg() argument
177 writel(DFI_INIT_START, &pctl->dfistcfg0); in dfi_cfg()
179 &pctl->dfistcfg1); in dfi_cfg()
180 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); in dfi_cfg()
182 &pctl->dfilpcfg0); in dfi_cfg()
184 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); in dfi_cfg()
185 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); in dfi_cfg()
186 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); in dfi_cfg()
187 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); in dfi_cfg()
[all …]
H A Dsdram_pctl_px30.c158 for (i = 0; pctl_regs->pctl[i][0] != 0xFFFFFFFF; i++) { in pctl_remodify_sdram_params()
159 if (pctl_regs->pctl[i][0] == 0) { in pctl_remodify_sdram_params()
160 tmp = pctl_regs->pctl[i][1];/* MSTR */ in pctl_remodify_sdram_params()
185 pctl_regs->pctl[tmp_adr][1] = tmp; in pctl_remodify_sdram_params()
195 for (i = 0; pctl_regs->pctl[i][0] != 0xFFFFFFFF; i++) { in pctl_cfg()
196 writel(pctl_regs->pctl[i][1], in pctl_cfg()
197 pctl_base + pctl_regs->pctl[i][0]); in pctl_cfg()
H A Dsdram_rv1126.c50 void __iomem *pctl; member
503 void __iomem *pctl_base = dram->pctl; in sw_set_req()
511 void __iomem *pctl_base = dram->pctl; in sw_set_ack()
527 void __iomem *pctl_base = dram->pctl; in set_ctl_address_map()
815 void __iomem *pctl_base = dram->pctl; in set_lp4_vref()
887 void __iomem *pctl_base = dram->pctl; in set_ds_odt()
1302 void __iomem *pctl_base = dram->pctl; in update_refresh_reg()
1319 void __iomem *pctl_base = dram->pctl; in read_mr()
1348 void __iomem *pctl_base = dram->pctl; in enter_sr()
1512 void __iomem *pctl_base = dram->pctl; in low_power_update()
[all …]
H A Dsdram_rk3328.c26 struct ddr_pctl_regs *pctl; member
223 void __iomem *pctl_base = dram->pctl; in set_ctl_address_map()
238 void __iomem *pctl_base = dram->pctl; in data_training()
247 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); in data_training()
251 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); in data_training()
325 void __iomem *pctl_base = dram->pctl; in enable_low_power()
348 void __iomem *pctl_base = dram->pctl; in sdram_init()
366 pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE); in sdram_init()
390 pctl_write_vrefdq(dram->pctl, 0x3, 5670, in sdram_init()
431 sdram_detect_bank(cap_info, dram->pctl, coltmp, bktmp); in dram_detect_cap()
[all …]
H A Dsdram_px30.c33 struct ddr_pctl_regs *pctl; member
173 void __iomem *pctl_base = dram->pctl; in set_ctl_address_map()
232 pctl_read_mr(dram->pctl, rank, mr_num); in read_mr()
276 void __iomem *pctl_base = dram->pctl; in data_training()
285 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); in data_training()
289 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); in data_training()
358 void __iomem *pctl_base = dram->pctl; in enable_low_power()
411 void __iomem *pctl_base = dram->pctl; in sdram_init_()
429 pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE); in sdram_init_()
444 pctl_write_mr(dram->pctl, 3, 11, 3, LPDDR3); in sdram_init_()
[all …]
H A Dsdram_rv1108.c206 clrsetbits_le32(&priv->pctl->mcfg, PD_IDLE_MASK, in enable_low_power()
208 clrsetbits_le32(&priv->pctl->mcfg1, in enable_low_power()
213 writel(GO_STATE, &priv->pctl->sctl); in enable_low_power()
238 sdram_priv->pctl = get_base_addr((void *)dtplat->reg, 0); in sdram_init()
H A Dsdram_rk3399.c30 struct rk3399_ddr_pctl_regs *pctl; member
144 u32 *denali_ctl = chan->pctl->denali_ctl; in set_memory_map()
213 denali_ctl = chan->pctl->denali_ctl; in phy_io_config()
553 denali_ctl = chan->pctl->denali_ctl; in set_ds_odt()
780 u32 *denali_ctl_0 = chan_0->pctl->denali_ctl; in pctl_start()
782 u32 *denali_ctl_1 = chan_1->pctl->denali_ctl; in pctl_start()
905 denali_ctl = chan->pctl->denali_ctl; in set_lp4_dq_odt()
964 denali_ctl = chan->pctl->denali_ctl; in set_lp4_ca_odt()
1023 denali_ctl = chan->pctl->denali_ctl; in set_lp4_MR3()
1081 denali_ctl = chan->pctl->denali_ctl; in set_lp4_MR12()
[all …]
H A Dsdram_rk3308.c709 priv->pctl->trfc = (tmp * nMHz + 999) / 1000; in modify_sdram_params()
713 priv->pctl->texsr = tmp & 0x3FF; in modify_sdram_params()
726 priv->pctl->trfc = (tmp * nMHz + 999) / 1000; in modify_sdram_params()
736 priv->pctl->trfc = (tmp * nMHz + 999) / 1000; in modify_sdram_params()
740 priv->pctl->texsr = tmp & 0x3FF; in modify_sdram_params()
839 clrsetbits_le32(&priv->pctl->mcfg, PD_IDLE_MASK, in enable_low_power()
841 clrsetbits_le32(&priv->pctl->mcfg1, in enable_low_power()
846 writel(GO_STATE, &priv->pctl->sctl); in enable_low_power()
863 sdram_priv.pctl = (void *)DDR_PCTL_BASE; in sdram_init()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c30 struct rk3036_ddr_pctl *pctl; member
443 static void send_command(struct rk3036_ddr_pctl *pctl, in send_command() argument
446 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
448 while (readl(&pctl->mcmd) & START_CMD) in send_command()
454 struct rk3036_ddr_pctl *pctl = priv->pctl; in memory_init() local
456 send_command(pctl, 3, DESELECT_CMD, 0); in memory_init()
458 send_command(pctl, 3, PREA_CMD, 0); in memory_init()
459 send_command(pctl, 3, MRS_CMD, in memory_init()
464 send_command(pctl, 3, MRS_CMD, in memory_init()
469 send_command(pctl, 3, MRS_CMD, in memory_init()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3066/
H A Dsdram_rk3066.c31 struct rk3288_ddr_pctl *pctl; member
175 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) in dfi_cfg() argument
177 writel(DFI_INIT_START, &pctl->dfistcfg0); in dfi_cfg()
179 &pctl->dfistcfg1); in dfi_cfg()
180 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); in dfi_cfg()
182 &pctl->dfilpcfg0); in dfi_cfg()
184 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); in dfi_cfg()
185 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); in dfi_cfg()
186 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); in dfi_cfg()
187 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); in dfi_cfg()
[all …]
/rk3399_rockchip-uboot/arch/arm/dts/
H A Drk3288-miqi.dts20 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
H A Drk3288-popmetal.dts20 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
H A Drk3288-fennec.dts20 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
H A Drk3288-evb.dts37 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
H A Drk3288-evb-rk1608.dts20 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
H A Drk3288-tinker.dts20 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
H A Drk3288-firefly.dts25 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_rv1108.h47 struct ddr_pctl *pctl; member
H A Dsdram_rk3308.h79 struct ddr_pctl *pctl; member
H A Dsdram_pctl_px30.h11 u32 pctl[35][2]; member
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt53 -rockchip,pctl-timing: parameters for the SDRAM setup, in this order:
146 rockchip,pctl-timing = <0x29a 0x1f4 0xc8 0x42 0x4e 0x4 0xea 0xa

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