106 	       &priv->pctl->mcmd);  in send_command()
107 	while (readl(&priv->pctl->mcmd) & START_CMD)  in send_command()
201 		state = readl(&priv->pctl->stat) & PCTL_CTL_STAT_MASK;  in move_to_config_state()
204 			writel(WAKEUP_STATE, &priv->pctl->sctl);  in move_to_config_state()
205 			while ((readl(&priv->pctl->stat) & PCTL_CTL_STAT_MASK)  in move_to_config_state()
214 			writel(CFG_STATE, &priv->pctl->sctl);  in move_to_config_state()
215 			while ((readl(&priv->pctl->stat) & PCTL_CTL_STAT_MASK)  in move_to_config_state()
232 		state = readl(&priv->pctl->stat) & PCTL_CTL_STAT_MASK;  in move_to_access_state()
235 			writel(WAKEUP_STATE, &priv->pctl->sctl);  in move_to_access_state()
236 			while ((readl(&priv->pctl->stat) &  in move_to_access_state()
241 			writel(CFG_STATE, &priv->pctl->sctl);  in move_to_access_state()
242 			while ((readl(&priv->pctl->stat) &  in move_to_access_state()
247 			writel(GO_STATE, &priv->pctl->sctl);  in move_to_access_state()
248 			while ((readl(&priv->pctl->stat) &  in move_to_access_state()
270 	       &priv->pctl->dfistcfg0);  in pctl_cfg()
274 	       &priv->pctl->dfistcfg1);  in pctl_cfg()
276 	       PARITY_INTR_EN << PARITY_INTR_EN_SHIFT, &priv->pctl->dfistcfg2);  in pctl_cfg()
278 	writel(TPHYUPD_TYPE0, &priv->pctl->dfitphyupdtype0);  in pctl_cfg()
279 	writel(TPHY_RDLAT, &priv->pctl->dfitphyrdlat);  in pctl_cfg()
280 	writel(TPHY_WRDATA, &priv->pctl->dfitphywrdata);  in pctl_cfg()
283 	       &priv->pctl->dfiupdcfg);  in pctl_cfg()
285 	copy_to_reg(&priv->pctl->togcnt1u,  in pctl_cfg()
298 		       &priv->pctl->dfiodtcfg);  in pctl_cfg()
301 		       &priv->pctl->dfiodtcfg1);  in pctl_cfg()
304 		       &priv->pctl->trsth);  in pctl_cfg()
311 			       &priv->pctl->mcfg);  in pctl_cfg()
318 			       &priv->pctl->mcfg);  in pctl_cfg()
325 			       &priv->pctl->mcfg);  in pctl_cfg()
329 		       &priv->pctl->dfilpcfg0);  in pctl_cfg()
331 		reg = readl(&priv->pctl->tcl);  in pctl_cfg()
332 		writel((reg - 1) / 2 - 1, &priv->pctl->dfitrddataen);  in pctl_cfg()
333 		reg = readl(&priv->pctl->tcwl);  in pctl_cfg()
334 		writel((reg - 1) / 2 - 1, &priv->pctl->dfitphywrlat);  in pctl_cfg()
342 		       &priv->pctl->dfiodtcfg);  in pctl_cfg()
345 		       &priv->pctl->dfiodtcfg1);  in pctl_cfg()
347 		writel(0, &priv->pctl->trsth);  in pctl_cfg()
351 		       PD_TYPE_ACT_PD | PD_IDLE_DISABLE, &priv->pctl->mcfg);  in pctl_cfg()
357 		       &priv->pctl->dfilpcfg0);  in pctl_cfg()
359 		reg = readl(&priv->pctl->tcl);  in pctl_cfg()
360 		writel(reg / 2 - 1, &priv->pctl->dfitrddataen);  in pctl_cfg()
361 		reg = readl(&priv->pctl->tcwl);  in pctl_cfg()
362 		writel(reg / 2 - 1, &priv->pctl->dfitphywrlat);  in pctl_cfg()
365 	setbits_le32(&priv->pctl->scfg, HW_LOW_POWER_EN);  in pctl_cfg()
368 	clrsetbits_le32(&priv->pctl->ppcfg, PPMEM_EN_MASK, PPMEM_EN);  in pctl_cfg()
421 	value = readl(&priv->pctl->trefi);  in data_training()
422 	writel(UPD_REF, &priv->pctl->trefi);  in data_training()
446 	writel(value | UPD_REF, &priv->pctl->trefi);  in data_training()
620 	writel(POWER_UP_START, &sdram_priv->pctl->powctl);  in rv1108_sdram_init()
621 	while (!(readl(&sdram_priv->pctl->powstat) & POWER_UP_DONE))  in rv1108_sdram_init()