30 	struct rk3399_ddr_pctl_regs *pctl;  member
144 	u32 *denali_ctl = chan->pctl->denali_ctl;  in set_memory_map()
213 		denali_ctl = chan->pctl->denali_ctl;  in phy_io_config()
553 		denali_ctl = chan->pctl->denali_ctl;  in set_ds_odt()
780 	u32 *denali_ctl_0 = chan_0->pctl->denali_ctl;  in pctl_start()
782 	u32 *denali_ctl_1 = chan_1->pctl->denali_ctl;  in pctl_start()
905 		denali_ctl = chan->pctl->denali_ctl;  in set_lp4_dq_odt()
964 		denali_ctl = chan->pctl->denali_ctl;  in set_lp4_ca_odt()
1023 		denali_ctl = chan->pctl->denali_ctl;  in set_lp4_MR3()
1081 		denali_ctl = chan->pctl->denali_ctl;  in set_lp4_MR12()
1141 		denali_ctl = chan->pctl->denali_ctl;  in set_lp4_MR14()
1244 	u32 *denali_ctl = chan->pctl->denali_ctl;  in pctl_cfg()
1402 	u32 *denali_ctl = chan->pctl->denali_ctl;  in override_write_leveling_value()
1838 			setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],  in dram_all_config()
2111 	u32 *denali_ctl = chan->pctl->denali_ctl;  in set_cap_relate_config()
2163 	u32 *denali_ctl = chan->pctl->denali_ctl;  in dram_set_cs()
2187 	u32 *denali_ctl = chan->pctl->denali_ctl;  in dram_set_bw()
2197 	u32 *denali_ctl = chan->pctl->denali_ctl;  in dram_set_max_col()
2224 	u32 *denali_ctl = chan->pctl->denali_ctl;  in dram_set_max_bank()
2241 	u32 *denali_ctl = chan->pctl->denali_ctl;  in dram_set_max_row()
2317 	sdram_detect_bank(cap_info, chan->pctl, col_tmp, bk_tmp);  in dram_detect_cap()
2397 	struct rk3399_ddr_pctl_regs *ddr_pctl_regs = chan->pctl;  in read_mr_for_detect()
2513 	denali_ctl = dram->chan[channel].pctl->denali_ctl;  in dram_copy_phy_fn()
2766 		read_mr(dram->chan[channel].pctl, 1, 5, &mr5);  in dram_copy_phy_fn()
3122 	priv->chan[0].pctl = regmap_get_range(plat->map, 0);  in rk3399_dmc_init()
3126 	priv->chan[1].pctl = regmap_get_range(plat->map, 4);  in rk3399_dmc_init()
3132 	      priv->chan[0].pctl, priv->chan[0].pi,  in rk3399_dmc_init()
3134 	      priv->chan[1].pctl, priv->chan[1].pi,  in rk3399_dmc_init()