drivers: ram: rockchip: Optimize some code commenting

Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I538fd61097841415ee6e113a46e9166e184a233b

Merge branch 'next-dev' into thunder-boot

driver: ram: rockchip: rename sdram_common.* to sdram.*

Change-Id: Idc6edee2906297d3ab681a36dc58c79283c0eb57
Signed-off-by: YouMin Chen <cym@rock-chips.com>

driver: ram: rk3288: rename sdram.h to sdram_rk3288.h

Change-Id: Ie7a7820d78397250f37917947b91cb940ffd5bda
Signed-off-by: YouMin Chen <cym@rock-chips.com>

rockchip: dmc: rk3368: update rank number for evb-px5

evb-px5 has only 1 CS, update for it.

Change-Id: I5393d21c88d44457a590cb31df31eb59d20bbf02
Signed-off-by: Kever Yang <kever.yang@rock-chips.com

rockchip: dmc: rk3368: update rank number for evb-px5

evb-px5 has only 1 CS, update for it.

Change-Id: I5393d21c88d44457a590cb31df31eb59d20bbf02
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>

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treewide: replace with error() with pr_err()

U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h

treewide: replace with error() with pr_err()

U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

# define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux. (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// <smpl>
@@@@
-error
+pr_err
(...)
// </smpl>

Change-Id: I921807c1770d36a91e692c48ab477558bb2ed0b8
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 9b643e312d528f291966c1f30b0d90bf3b1d43dc)

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UPSTREAM: rockchip: rk3368: adjust DMC driver for 32/64bit-aware OF_PLATDATA

With the new 32/64bit-aware dtoc, the type of reg is fdt64_t and the
OF_PLATDATA structure layout changes. This adjusts

UPSTREAM: rockchip: rk3368: adjust DMC driver for 32/64bit-aware OF_PLATDATA

With the new 32/64bit-aware dtoc, the type of reg is fdt64_t and the
OF_PLATDATA structure layout changes. This adjusts the DMC driver for
the RK3368 to track these changes.

For the time being (i.e. until regmap_init_mem_platdata works for the
64bit case), we won't use regmap_init_mem_platdata here and simply
access of_plat.reg[] directly.

Change-Id: I9e4e5b7cb650220902914f6ad724a8a312be93ba
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 1d70f0ac88dcd0ed9c17ec4c5e97db69de961319)

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Merge branch 'master' of git://git.denx.de/u-boot-rockchip

rockchip: rk3368: add DRAM controller driver with DRAM initialisation

This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM control

rockchip: rk3368: add DRAM controller driver with DRAM initialisation

This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).

At this stage, only the following feature-set is supported:
- DDR3
- 32-bit configuration (i.e. fully populated)
- dual-rank (i.e. no auto-detection of ranks)
- DDR3-1600K speed-bin

This driver expects to run from a TPL stage that will later return to
the RK3368 BROM. It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
init code).

Unlike other DMC drivers for RK32xx and RK33xx parts, the required
timings are calculated within the driver based on a target frequency
and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
time).

The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
register for controlling the operation of its (single-channel) DRAM
controller in the GRF block. This provides for selecting DDR3, mobile
DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure
definition (at offset 0x600).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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