Lines Matching refs:pctl
50 void __iomem *pctl; member
503 void __iomem *pctl_base = dram->pctl; in sw_set_req()
511 void __iomem *pctl_base = dram->pctl; in sw_set_ack()
527 void __iomem *pctl_base = dram->pctl; in set_ctl_address_map()
815 void __iomem *pctl_base = dram->pctl; in set_lp4_vref()
887 void __iomem *pctl_base = dram->pctl; in set_ds_odt()
1302 void __iomem *pctl_base = dram->pctl; in update_refresh_reg()
1319 void __iomem *pctl_base = dram->pctl; in read_mr()
1348 void __iomem *pctl_base = dram->pctl; in enter_sr()
1512 void __iomem *pctl_base = dram->pctl; in low_power_update()
1580 void __iomem *pctl_base = dram->pctl; in data_training_rg()
1596 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); in data_training_rg()
1619 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); in data_training_rg()
1642 void __iomem *pctl_base = dram->pctl; in data_training_wl()
1649 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); in data_training_wl()
1660 pctl_write_mr(dram->pctl, (cs + 1) & 1, 1, tmp | (1 << 12), in data_training_wl()
1694 pctl_write_mr(dram->pctl, (cs + 1) & 1, 1, tmp & ~(1 << 12), in data_training_wl()
1697 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); in data_training_wl()
1712 void __iomem *pctl_base = dram->pctl; in data_training_rd()
1743 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); in data_training_rd()
1811 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); in data_training_rd()
1829 void __iomem *pctl_base = dram->pctl; in data_training_wr()
1845 pctl_write_mr(dram->pctl, 3, 2, 0x6, dramtype); in data_training_wr()
1848 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); in data_training_wr()
1892 send_a_refresh(dram->pctl, 0x3); in data_training_wr()
1915 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); in data_training_wr()
1932 pctl_write_mr(dram->pctl, 3, 2, mr_tmp & PCTL2_MR_MASK, in data_training_wr()
2222 void __iomem *pctl_base = dram->pctl; in update_noc_timing()
2332 void __iomem *pctl_base = dram->pctl; in dram_all_config()
2363 void __iomem *pctl_base = dram->pctl; in enable_low_power()
2396 void __iomem *pctl_base = dram->pctl; in ddr_set_atags()
2569 void __iomem *pctl_base = dram->pctl; in sdram_init_()
2587 pctl_cfg(dram->pctl, &sdram_params->pctl_regs, in sdram_init_()
2631 pctl_write_mr(dram->pctl, 3, 11, lp3_odt_value, LPDDR3); in sdram_init_()
2636 pctl_write_mr(dram->pctl, 3, 11, in sdram_init_()
2640 pctl_write_mr(dram->pctl, 3, 12, in sdram_init_()
2646 pctl_write_mr(dram->pctl, 3, 22, in sdram_init_()
2651 pctl_write_mr(dram->pctl, 0x3, 6, mr_tmp | BIT(7), DDR4); in sdram_init_()
2652 pctl_write_mr(dram->pctl, 0x3, 6, mr_tmp | BIT(7), DDR4); in sdram_init_()
2653 pctl_write_mr(dram->pctl, 0x3, 6, mr_tmp, DDR4); in sdram_init_()
2685 pctl_write_mr(dram->pctl, 3, 14, in sdram_init_()
2699 pctl_write_vrefdq(dram->pctl, 0x3, ddr4_vref, in sdram_init_()
2714 void __iomem *pctl_base = dram->pctl; in dram_detect_cap()
2840 void __iomem *pctl_base = dram->pctl; in dram_detect_cs1_row()
3015 void __iomem *pctl_base = dram->pctl; in pre_set_rate()
3024 for (j = find; sdram_params->pctl_regs.pctl[j][0] != 0xFFFFFFFF; in pre_set_rate()
3026 if (sdram_params->pctl_regs.pctl[j][0] == in pre_set_rate()
3028 writel(sdram_params->pctl_regs.pctl[j][1], in pre_set_rate()
3073 pctl_write_mr(dram->pctl, 3, 13, in pre_set_rate()
3082 pctl_write_mr(dram->pctl, 3, 3, in pre_set_rate()
3092 pctl_write_mr(dram->pctl, 3, 1, in pre_set_rate()
3099 pctl_write_mr(dram->pctl, 3, 2, mr_tmp & PCTL2_MR_MASK, in pre_set_rate()
3107 pctl_write_mr(dram->pctl, 3, 11, in pre_set_rate()
3113 pctl_write_mr(dram->pctl, 3, 12, in pre_set_rate()
3120 pctl_write_mr(dram->pctl, 3, 22, in pre_set_rate()
3126 pctl_write_mr(dram->pctl, 3, 14, in pre_set_rate()
3139 void __iomem *pctl_base = dram->pctl; in save_fsp_param()
3333 for (int i = 0; pctl_regs->pctl[i][0] != 0xffffffff; i++) { in pctl_modify_trfc()
3334 switch (pctl_regs->pctl[i][0]) { in pctl_modify_trfc()
3336 tmp = pctl_regs->pctl[i][1]; in pctl_modify_trfc()
3340 pctl_regs->pctl[i][1] = tmp; in pctl_modify_trfc()
3345 tmp = pctl_regs->pctl[i][1]; in pctl_modify_trfc()
3359 pctl_regs->pctl[i][1] = tmp; in pctl_modify_trfc()
3366 tmp = pctl_regs->pctl[i][1]; in pctl_modify_trfc()
3370 pctl_regs->pctl[i][1] = tmp; in pctl_modify_trfc()
3390 void __iomem *pctl_base = dram->pctl; in ddr_set_rate()
3429 pctl_write_mr(dram->pctl, 2, 1, cur_init3, dramtype); in ddr_set_rate()
3504 pctl_write_mr(dram->pctl, 3, 1, in ddr_set_rate()
3508 pctl_write_mr(dram->pctl, 3, 2, dst_init3 & PCTL2_MR_MASK, in ddr_set_rate()
3510 pctl_write_mr(dram->pctl, 3, 3, in ddr_set_rate()
3514 pctl_write_mr(dram->pctl, 3, 11, lp3_odt_value, dramtype); in ddr_set_rate()
3516 pctl_write_mr(dram->pctl, 3, 1, dst_init3 & PCTL2_MR_MASK, in ddr_set_rate()
3519 pctl_write_mr(dram->pctl, 3, 0, in ddr_set_rate()
3525 pctl_write_mr(dram->pctl, 3, 0, in ddr_set_rate()
3529 pctl_write_mr(dram->pctl, 3, 2, in ddr_set_rate()
3533 pctl_write_mr(dram->pctl, 3, 3, mr_tmp & PCTL2_MR_MASK, in ddr_set_rate()
3537 pctl_write_mr(dram->pctl, 3, 4, in ddr_set_rate()
3541 pctl_write_mr(dram->pctl, 3, 5, in ddr_set_rate()
3549 pctl_write_mr(dram->pctl, 3, 6, in ddr_set_rate()
3552 pctl_write_mr(dram->pctl, 3, 6, in ddr_set_rate()
3555 pctl_write_mr(dram->pctl, 3, 6, in ddr_set_rate()
3561 pctl_write_mr(dram->pctl, 3, 13, in ddr_set_rate()
3656 dram_info.pctl = (void *)UPCTL2_BASE_ADDR; in sdram_init()
3700 sdram_params->pctl_regs.pctl[0][1] |= 0x1 << 10; in sdram_init()
3702 sdram_params->pctl_regs.pctl[0][1] &= in sdram_init()