Searched refs:mr0 (Results 1 – 18 of 18) sorted by relevance
| /rk3399_rockchip-uboot/board/ti/ks2_evm/ |
| H A D | ddr3_k2g.c | 30 .mr0 = 0x00001430ul,
81 .mr0 = 0x00001430ul,
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| H A D | ddr3_cfg.c | 29 .mr0 = 0x00001C70ul,
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| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a23.c | 38 .mr0 = 6736,
115 writel(dram_para.mr0, &mctl_phy->mr0); in mctl_init()
201 writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3); in mctl_init()
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| H A D | dram_sun8i_a83t.c | 135 writel(MCTL_MR0, &mctl_ctl->mr0); in auto_set_timing_para()
140 writel(MCTL_LPDDR3_MR0, &mctl_ctl->mr0); in auto_set_timing_para()
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| H A D | dram_sun8i_a33.c | 134 writel(MCTL_MR0, &mctl_ctl->mr0); in auto_set_timing_para()
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| H A D | dram_sun6i.c | 123 writel(MCTL_MR0, &mctl_phy->mr0); in mctl_channel_init()
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| H A D | dram_sun9i.c | 635 writel(mr[0], &mctl_phy->mr0); in mctl_channel_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-keystone/include/mach/ |
| H A D | ddr3.h | 29 unsigned int mr0; member
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_rv1108_pctl_phy.c | 114 u32 mr0; in memory_init() local
138 mr0 = params_priv->ddr_timing_t.phy_timing.mr[0]; in memory_init()
142 (((mr0 | DDR3_DLL_RESET) & in memory_init()
149 (((mr0 | DDR3_DLL_RESET) & in memory_init()
157 ((mr0 & CMD_ADDR_MASK) << in memory_init()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun8i_a23.h | 25 u32 mr0; member
185 u32 mr0; /* 0x54 mode register 0 */ member
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| H A D | dram_sun8i_a33.h | 75 u32 mr0; /* 0x30 */ member
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| H A D | dram_sun8i_a83t.h | 75 u32 mr0; /* 0x30 */ member
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| H A D | dram_sun9i.h | 108 u32 mr0; /* 0x9c mode register 0 */ member
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| H A D | dram_sun6i.h | 174 u32 mr0; /* 0x40 mode register 0 */ member
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| /rk3399_rockchip-uboot/arch/arm/mach-keystone/ |
| H A D | ddr3_spd.c | 35 debug_ddr_cfg("mr0 0x%08X\n", ptr->mr0); in dump_phy_config()
347 spd_cb->phy_cfg.mr0 = 1 << 12 | (spd->t_wr_bin & 0x7) << 9 | 0 << 8 | in init_ddr3param()
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| H A D | ddr3.c | 53 __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET); in ddr3_init_ddrphy()
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| /rk3399_rockchip-uboot/arch/nds32/cpu/n1213/ |
| H A D | start.S | 130 mfsr $r1, $mr0
132 mtsr $r1, $mr0
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/clock/ |
| H A D | rockchip,rk3288-dmc.txt | 92 mr0..mr3
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