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Searched refs:mfspr (Results 1 – 25 of 25) sorted by relevance

/rk3399_rockchip-uboot/arch/powerpc/lib/
H A Dbat_rw.c130 l = mfspr (DBAT0L); in read_bat()
131 u = mfspr (DBAT0U); in read_bat()
134 l = mfspr (IBAT0L); in read_bat()
135 u = mfspr (IBAT0U); in read_bat()
138 l = mfspr (DBAT1L); in read_bat()
139 u = mfspr (DBAT1U); in read_bat()
142 l = mfspr (IBAT1L); in read_bat()
143 u = mfspr (IBAT1U); in read_bat()
146 l = mfspr (DBAT2L); in read_bat()
147 u = mfspr (DBAT2U); in read_bat()
[all …]
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc86xx/
H A Drelease.S31 mfspr r0, MSSCR0
59 mfspr r0, HID0
76 mfspr r3, l2cr
80 mfspr r3, l2cr
89 1: mfspr r3, l2cr
94 mfspr r3, l2cr
101 mfspr r3, HID0
120 mfspr r3, HID0
131 mfspr r4, HID0
138 mfspr r4, HID1
H A Dcache.S36 mfspr r3,HID0
46 mfspr r3,HID0
175 mfspr r3, HID0
193 mfspr r3, HID0
205 mfspr r3, HID0
211 mfspr r3, HID0
227 mfspr r3, HID0
254 mfspr r3, HID0
272 mfspr r3, HID0
280 mfspr r3, l2cr
[all …]
H A Dstart.S88 mfspr r4,DAR
90 mfspr r5,DSISR
867 mfspr r0, HID0
918 mfspr r0, HID0
927 mfspr r0, LDSTCR
954 mfspr r0, HID0
966 mfspr r0, LDSTCR
H A Dcpu.c41 uint msscr0 = mfspr(MSSCR0); in checkcpu()
H A Dtraps.c117 printf("MSS error. MSSSR0: %08x\n", mfspr(SPRN_MSSSR0)); in MachineCheckException()
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/
H A Dtlb.c53 _mas1 = mfspr(MAS1); in read_tlbcam_entry()
57 *epn = mfspr(MAS2) & MAS2_EPN; in read_tlbcam_entry()
58 *rpn = mfspr(MAS3) & MAS3_RPN; in read_tlbcam_entry()
60 *rpn |= ((u64)mfspr(MAS7)) << 32; in read_tlbcam_entry()
67 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; in print_tlbcam()
103 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; in init_used_tlb_cams()
112 if (mfspr(MAS1) & MAS1_VALID) in init_used_tlb_cams()
146 if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 && in set_tlb()
208 _mas0 = mfspr(MAS0); in find_tlb_idx()
209 _mas1 = mfspr(MAS1); in find_tlb_idx()
[all …]
H A Drelease.S42 mfspr r0,PVR
53 mfspr r3,SPRN_HDBCR1
59 mfspr r3,SPRN_SVR
77 mfspr r3,SPRN_HDBCR0
100 mfspr r3,SPRN_L1CSR1
109 mfspr r3,SPRN_L1CSR1
118 mfspr r3,SPRN_L1CSR0
127 mfspr r3,SPRN_L1CSR0
138 mfspr r0,SPRN_PIR
201 mfspr r3,SPRN_SVR
[all …]
H A Dstart.S91 mfspr r3,SPRN_SVR
111 mfspr r3,SPRN_HDBCR0
121 mfspr r3, SPRN_HDBCR0
135 mfspr r3, SPRN_L2CSR0
141 mfspr r3, SPRN_L2CSR0
151 mfspr r3, SPRN_L2CSR0
155 mfspr r3, SPRN_L2CSR0
174 mfspr r1,DBSR
316 mfspr r3,PVR
327 mfspr r3,SPRN_HDBCR1
[all …]
H A Dspl_minimal.c42 u32 s = mfspr(SPRN_TBRL); in udelay()
44 while ((mfspr(SPRN_TBRL) - s) < ticks); in udelay()
H A Dtraps.c144 mcsrr0 = mfspr(SPRN_MCSRR0); in MachineCheckException()
145 mcsrr1 = mfspr(SPRN_MCSRR1); in MachineCheckException()
146 mcsr = mfspr(SPRN_MCSR); in MachineCheckException()
147 mcar = mfspr(SPRN_MCAR); in MachineCheckException()
H A Dcpu_init.c683 u32 l2cfg0 = mfspr(SPRN_L2CFG0); in l2cache_init()
687 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) in l2cache_init()
699 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) in l2cache_init()
776 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); in cpu_init_r()
783 mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID)); in cpu_init_r()
792 if (mfspr(L1CSR2) & L1CSR2_DCWS) in cpu_init_r()
793 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); in cpu_init_r()
H A Dinterrupts.c45 mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE); in interrupt_init_cpu()
H A Dfdt.c294 u32 l2cfg0 = mfspr(SPRN_L2CFG0); in ft_fixup_l2cache()
387 u32 l1cfg0 = mfspr(SPRN_L1CFG0); in ft_fixup_cache()
388 u32 l1cfg1 = mfspr(SPRN_L1CFG1); in ft_fixup_cache()
492 svr = mfspr(SPRN_SVR); in ft_fixup_qe_snum()
H A Dcpu.c309 val = mfspr(DBCR0); in do_reset()
346 mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) | in init_85xx_watchdog()
H A Dmp.c24 return mfspr(SPRN_PIR); in get_my_id()
/rk3399_rockchip-uboot/arch/powerpc/include/asm/
H A Dppc.h46 uint immr = mfspr(SPRN_IMMR); in get_immr()
53 return mfspr(PVR); in get_pvr()
58 return mfspr(SVR); in get_svr()
H A Dcache.h114 return mfspr(IC_CST); in rd_ic_cst()
129 return mfspr(DC_CST); in rd_dc_cst()
H A Dprocessor.h1151 #define mfspr(rn) ({unsigned int rval; \ macro
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc8xx/
H A Dcache.c16 return !!(mfspr(IC_CST) & IDC_ENABLED); in icache_status()
34 return !!(mfspr(IC_CST) & IDC_ENABLED); in dcache_status()
H A Dstart.S82 mfspr r3, ICR /* clear Interrupt Cause Register */
95 mfspr r3, IC_CST /* Clear error bits */
96 mfspr r3, DC_CST
188 mfspr r4,DAR
190 mfspr r5,DSISR
/rk3399_rockchip-uboot/include/
H A Dppc_asm.tmpl173 mfspr r20,SPRG0; \
175 mfspr r22,SPRG1; \
181 mfspr r20,XER; \
183 mfspr r20, DAR_DEAR; \
185 mfspr r22,reg1; \
186 mfspr r23,reg2; \
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc83xx/
H A Dstart.S330 mfspr r4,DAR
332 mfspr r5,DSISR
739 mfspr r3, HID0
752 mfspr r3, HID0
762 mfspr r3, HID0
769 mfspr r3, HID0
781 mfspr r3, HID0
794 mfspr r3, HID0
1079 mfspr r0, HID0
1103 mfspr r3, HID0
/rk3399_rockchip-uboot/board/keymile/km83xx/
H A Dkm83xx.c158 svid = SVR_REV(mfspr(SVR)); in board_early_init_r()
/rk3399_rockchip-uboot/doc/
H A DREADME.POST499 register will be checked as well (using mfspr). To verify the bc