1b9735cbaSScott Wood /* 2b9735cbaSScott Wood * Copyright 2009 Freescale Semiconductor, Inc. 3b9735cbaSScott Wood * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 5b9735cbaSScott Wood */ 6b9735cbaSScott Wood 7b9735cbaSScott Wood #include <common.h> 8b9735cbaSScott Wood #include <asm/processor.h> 9b9735cbaSScott Wood #include <asm/global_data.h> 100b66513bSYork Sun #include <fsl_ifc.h> 11b9735cbaSScott Wood #include <asm/io.h> 12b9735cbaSScott Wood 13b9735cbaSScott Wood DECLARE_GLOBAL_DATA_PTR; 14b9735cbaSScott Wood cpu_init_f(void)15*701e6401SYork Sunulong cpu_init_f(void) 16b9735cbaSScott Wood { 17c97cd1baSScott Wood #ifdef CONFIG_SYS_INIT_L2_ADDR 18b9735cbaSScott Wood ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 19b9735cbaSScott Wood 20b9735cbaSScott Wood out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); 21b9735cbaSScott Wood 22b9735cbaSScott Wood /* set MBECCDIS=1, SBECCDIS=1 */ 23b9735cbaSScott Wood out_be32(&l2cache->l2errdis, 24b9735cbaSScott Wood (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); 25b9735cbaSScott Wood 26b9735cbaSScott Wood /* set L2E=1 & L2SRAM=001 */ 27b9735cbaSScott Wood out_be32(&l2cache->l2ctl, 28b9735cbaSScott Wood (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); 29b9735cbaSScott Wood #endif 30*701e6401SYork Sun 31*701e6401SYork Sun return 0; 32b9735cbaSScott Wood } 33b9735cbaSScott Wood 34b9735cbaSScott Wood #ifndef CONFIG_SYS_FSL_TBCLK_DIV 35b9735cbaSScott Wood #define CONFIG_SYS_FSL_TBCLK_DIV 8 36b9735cbaSScott Wood #endif 37b9735cbaSScott Wood udelay(unsigned long usec)38b9735cbaSScott Woodvoid udelay(unsigned long usec) 39b9735cbaSScott Wood { 40b9735cbaSScott Wood u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000); 41b9735cbaSScott Wood u32 ticks = ticks_per_usec * usec; 42b9735cbaSScott Wood u32 s = mfspr(SPRN_TBRL); 43b9735cbaSScott Wood 44b9735cbaSScott Wood while ((mfspr(SPRN_TBRL) - s) < ticks); 45b9735cbaSScott Wood } 46