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Searched refs:mcr (Results 1 – 25 of 63) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Darm32_macros.S25 mcr p15, 0, \reg, c1, c0, 0
29 mcr p15, 0, \reg, c1, c0, 1
37 mcr p15, 0, \reg, c1, c0, 2
49 mcr p15, 0, \reg, c1, c1, 0
53 mcr p15, 0, \reg, c1, c1, 2
61 mcr p15, 0, \reg, c2, c0, 0
69 mcr p15, 0, \reg, c2, c0, 1
77 mcr p15, 0, \reg, c2, c0, 2
86 mcr p15, 0, \reg, c3, c0, 0
102 mcr p15, 0, r0, c7, c1, 0
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/pxa/
H A Dstart.S102 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
103 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
112 mcr p15, 0, r0, c1, c0, 0
132 mcr p15, 0, r0, c3, c0, 0
136 mcr p15, 0, r0, c2, c0, 0
144 mcr p15, 0, r0, c1, c0, 0
148 mcr p15, 0, r0, c9, c1, 1
149 mcr p15, 0, r0, c9, c2, 1
152 mcr p15, 0, r0, c7, c7, 0
155 mcr p15, 0, r0, c10, c4, 1
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-mvebu/
H A Dlowlevel_spl.S32 mcr p15, 0, r0, c7, c6, 1
48 mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
49 mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
50 mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
67 mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/
H A Dstart.S70 mcr p15, 0, r0, c1, c0, 1
81 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
85 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
110 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
111 mcr p15, 0, r0, c7, c10, 4 @ DSB
112 mcr p15, 0, r0, c7, c5, 4 @ ISB
155 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
156 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
157 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
158 mcr p15, 0, r0, c7, c10, 4 @ DSB
[all …]
H A Dnonsec_virt.S49 mcr p15, 0, r5, c12, c0, 1
64 mcr p15, 0, r5, c1, c0, 1
71 mcr p15, 0, r5, c1, c0, 1
86 mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set)
183 mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec
200 mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors
H A Dpsci.S160 mcr p15, 0, r4, c1, c1, 0
176 2: mcr p15, 0, r7, c1, c1, 0
205 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
221 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
235 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
245 mcr p15, 0, r0, c1, c0, 1 @ ACTLR
255 mcr p15, 0, r0, c1, c0, 1 @ ACTLR
270 mcr p15, 0, r0, c1, c0, 0 @ SCTLR
H A Dcache_v7_asm.S41 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
60 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
74 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
114 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
133 mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
144 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx35/
H A Dlowlevel_macro.S104 mcr p15, 0, r0, c1, c0, 1
113 mcr p15, 0, r1, c1, c0, 0
117 mcr p15, 0, r0, c15, c2, 4
119 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */
120 mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */
121 mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */
125 mcr p15, 0, r0, c15, c2, 4
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-armv7/
H A Dgenerictimer.h35 mcr p15, 0, \reg, c14, c2, 0
38 mcr p15, 0, \reg, c14, c2, 1
44 mcr p15, 0, \reg, c14, c2, 1
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/spear/
H A Dstart.S65 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
66 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
73 mcr p15, 0, r0, c1, c0, 0
/rk3399_rockchip-uboot/drivers/spi/
H A Dfsl_qspi.c373 reg = qspi_read32(priv->flags, &regs->mcr); in qspi_ahb_invalid()
375 qspi_write32(priv->flags, &regs->mcr, reg); in qspi_ahb_invalid()
384 qspi_write32(priv->flags, &regs->mcr, reg); in qspi_ahb_invalid()
394 mcr_reg = qspi_read32(priv->flags, &regs->mcr); in qspi_ahb_read()
396 qspi_write32(priv->flags, &regs->mcr, in qspi_ahb_read()
404 qspi_write32(priv->flags, &regs->mcr, mcr_reg); in qspi_ahb_read()
412 reg = qspi_read32(priv->flags, &regs->mcr); in qspi_enable_ddr_mode()
414 qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK); in qspi_enable_ddr_mode()
427 qspi_write32(priv->flags, &regs->mcr, reg); in qspi_enable_ddr_mode()
478 mcr_reg = qspi_read32(priv->flags, &regs->mcr); in qspi_op_rdbank()
[all …]
/rk3399_rockchip-uboot/drivers/i2c/
H A Dimx_lpi2c.c64 val = readl(&regs->mcr); in imx_lpci2c_check_clear_error()
66 writel(val, &regs->mcr); in imx_lpci2c_check_clear_error()
265 mode = (readl(&regs->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT; in bus_i2c_set_bus_speed()
267 val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK; in bus_i2c_set_bus_speed()
268 writel(val | LPI2C_MCR_MEN(0), &regs->mcr); in bus_i2c_set_bus_speed()
310 val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK; in bus_i2c_set_bus_speed()
311 writel(val | LPI2C_MCR_MEN(1), &regs->mcr); in bus_i2c_set_bus_speed()
325 writel(LPI2C_MCR_RST_MASK, &regs->mcr); in bus_i2c_init()
326 writel(0x0, &regs->mcr); in bus_i2c_init()
328 writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), &regs->mcr); in bus_i2c_init()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm946es/
H A Dstart.S80 mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */
81 mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */
91 mcr p15, 0, r0, c1, c0, 0
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/arm32/
H A Dlowlevel_init.S26 mcr p15, 0, r0, c1, c0, 0
45 mcr p15, 0, r0, c1, c0, 0
57 mcr p15, 0, r0, c2, c0, 2
60 mcr p15, 0, r0, c2, c0, 0 @ TTBR0
63 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
66 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
77 mcr p15, 0, r0, c1, c0, 0
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/
H A Dstart.S83 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
84 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
102 mcr p15, 0, r0, c1, c0, 0
/rk3399_rockchip-uboot/arch/arm/cpu/arm1136/
H A Dstart.S72 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
73 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
83 mcr p15, 0, r0, c1, c0, 0
/rk3399_rockchip-uboot/arch/arm/cpu/arm1176/
H A Dstart.S78 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
79 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
98 mcr p15, 0, r0, c1, c0, 0
/rk3399_rockchip-uboot/arch/arm/cpu/arm920t/
H A Dstart.S88 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
89 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
99 mcr p15, 0, r0, c1, c0, 0
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/sunxi/
H A Dfel_utils.S34 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
36 mcr p15, 0, r1, c12, c0, 0 @ Write VBAR
38 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
/rk3399_rockchip-uboot/arch/arm/cpu/sa1100/
H A Dstart.S118 mcr p15,0,r0,c1,c0
124 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
125 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/rk3399_rockchip-uboot/arch/arm/lib/
H A Drelocate.S45 mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
119 mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */
120 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c74 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
76 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
80 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
82 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
104 clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28), in mctl_set_drive()
106 clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), in mctl_set_drive()
411 setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); in dramc_clock_output_en()
413 clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); in dramc_clock_output_en()
/rk3399_rockchip-uboot/drivers/crypto/fsl/
H A Djr.c568 uint32_t mcr = sec_in32(&sec->mcfgr); in sec_init_idx() local
590 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT); in sec_init_idx()
591 mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT); in sec_init_idx()
593 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); in sec_init_idx()
597 mcr |= (1 << MCFGR_PS_SHIFT); in sec_init_idx()
599 sec_out32(&sec->mcfgr, mcr); in sec_init_idx()
/rk3399_rockchip-uboot/cmd/ddr_tool/
H A Dddr_tool_mp.S45 mcr p15, 0, r0, c1, c0, 0 /* for remap VBAR */
47 mcr p15, 0, r0, c12, c0, 0
60 mcr p15, 0, r0, c7, c5, 0
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mx25/
H A Dgeneric.c106 ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() : in imx_get_perclk()
129 setbits_le32(&ccm->mcr, 1 << clk); in imx_set_perclk()
131 clrbits_le32(&ccm->mcr, 1 << clk); in imx_set_perclk()

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